+2006-07-27 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ PR gcc/28508
+ * config/m32r/m32r.md (branch_insn): Reduce pc range for short
+ branch.
+ (rev_branch_insn): Likewise.
+
2006-07-27 Jan Hubicka <jh@suse.cz>
PR rtl-optimization/28071
return instruction;
}"
[(set_attr "type" "branch")
- ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+ ; cf PR gcc/28508
+ ; We use 300/600 instead of 512,1024 to account for inaccurate insn
; lengths and insn alignments that are complex to track.
; It's not important that we be hyper-precise here. It may be more
; important blah blah blah when the chip supports parallel execution
; blah blah blah but until then blah blah blah this is simple and
; suffices.
(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
- (const_int 400))
- (const_int 800))
+ (const_int 300))
+ (const_int 600))
(const_int 2)
(const_int 4)))])
return instruction;
}"
[(set_attr "type" "branch")
- ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+ ; cf PR gcc/28508
+ ; We use 300/600 instead of 512,1024 to account for inaccurate insn
; lengths and insn alignments that are complex to track.
; It's not important that we be hyper-precise here. It may be more
; important blah blah blah when the chip supports parallel execution
; blah blah blah but until then blah blah blah this is simple and
; suffices.
(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
- (const_int 400))
- (const_int 800))
+ (const_int 300))
+ (const_int 600))
(const_int 2)
(const_int 4)))])