Added peephole definitions for Load/Store Base insns and eliminating

redundant load in an equivalent store/load sequence.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@10278 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md
index b50b35b..2032e23 100644 (file)
--- a/gcc/config/1750a/1750a.md
+++ b/gcc/config/1750a/1750a.md
@@ -1275,5 +1275,59 @@
   "INTVAL(operands[2]) == -1"
   "soj r%0,%3")
 
+;; Load Base
+(define_peephole 
+  [(set (match_operand:QI 0 "register_operand" "=r")
+        (mem:QI (plus:QI (match_operand:QI 1 "register_operand" "x")
+                         (match_operand:QI 2 "immediate_operand" "L"))))
+   ]
+  "REGNO(operands[0]) == 2 && REGNO(operands[1]) >= 12
+    && INTVAL(operands[2]) <= 255"
+  "lb r%1,%2")
+
+;; Double Load Base
+(define_peephole 
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (mem:HI (plus:QI (match_operand:QI 1 "register_operand" "x")
+                         (match_operand:QI 2 "immediate_operand" "L"))))
+   ]
+  "REGNO(operands[0]) == 0 && REGNO(operands[1]) >= 12
+    && INTVAL(operands[2]) <= 255"
+  "dlb r%1,%2")
+
+;; Store Base
+(define_peephole 
+  [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "x")
+                         (match_operand:QI 1 "immediate_operand" "L")))
+       (match_operand:QI 2 "register_operand" "r"))
+   ]
+  "REGNO(operands[2]) == 2 && REGNO(operands[0]) >= 12
+    && INTVAL(operands[1]) <= 255"
+  "stb r%0,%1")
+
+;; Double Store Base
+(define_peephole 
+  [(set (mem:HI (plus:QI (match_operand:QI 0 "register_operand" "x")
+                         (match_operand:QI 1 "immediate_operand" "L")))
+       (match_operand:HI 2 "register_operand" "r"))
+   ]
+  "REGNO(operands[2]) == 0 && REGNO(operands[0]) >= 12
+    && INTVAL(operands[1]) <= 255"
+  "stb r%0,%1")
+
+;; Eliminate the redundant load in a store/load sequence
+(define_peephole 
+  [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
+                         (match_operand:QI 1 "immediate_operand" "i")))
+       (match_operand:QI 2 "register_operand" "r"))
+   (set (match_operand:QI 3 "register_operand" "=r")
+       (mem:QI (plus:QI (match_operand:QI 4 "register_operand" "r")
+                        (match_operand:QI 5 "immediate_operand" "i"))))
+   ]
+  "REGNO(operands[2]) == REGNO(operands[3]) &&
+   REGNO(operands[0]) == REGNO(operands[4]) &&
+   INTVAL(operands[1]) == INTVAL(operands[5])"
+  "st r%2,%1,r%0  ; eliminated previous redundant load")
+
 ;;;End.