2011-05-04 Stuart Henderson <shenders@gcc.gnu.org>

        From Bernd Schmidt
        * config/bfin/bfin.md (addsi3): Add an alternative for IREGS.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173368 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 287615e..cd2b35a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2011-05-04  Stuart Henderson  <shenders@gcc.gnu.org>
+
+       From Bernd Schmidt
+       * config/bfin/bfin.md (addsi3): Add an alternative for IREGS.
+
 2011-05-04  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        * config/alpha/alpha.h (CODE_MASK, MIPS_IS_STAB, MIPS_MARK_STAB)

diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index c4722d4..903c8bb 100644 (file)
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -1217,22 +1217,21 @@
   "%0 = %h2 * %h1 (IS,M)%!"
   [(set_attr "type" "dsp32")])
 
-;; The processor also supports ireg += mreg or ireg -= mreg, but these
-;; are unusable if we don't ensure that the corresponding lreg is zero.
-;; The same applies to the add/subtract constant versions involving
-;; iregs
+;; The alternative involving IREGS requires that the corresponding L register
+;; is zero.
 
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
-       (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
-                (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
+  [(set (match_operand:SI 0 "register_operand" "=ad,a,d,b")
+       (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d,0")
+                (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d,fP2P4")))]
   ""
   "@
    %0 += %2;
    %0 = %1 + %2;
-   %0 = %1 + %2;"
+   %0 = %1 + %2;
+   %0 += %2;"
   [(set_attr "type" "alu0")
-   (set_attr "length" "2,2,2")])
+   (set_attr "length" "2,2,2,2")])
 
 (define_insn "ssaddsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")