.:

	PR rtl-optimization/17104
	* config/rs6000/rs6000.c (rs6000_emit_move): Don't wrap small
	loads in zero_extend.
testsuite:
	PR rtl-optimization/17104
	* gcc.dg/ppc-bitfield1.c: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@89980 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e5d2958..f581d1a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2004-11-02  Nathan Sidwell  <nathan@codesourcery.com>
+
+       PR rtl-optimization/17104
+       * config/rs6000/rs6000.c (rs6000_emit_move): Don't wrap small
+       loads in zero_extend.
+
 2004-11-02  Danny Smith  <dannysmith@users.sourceforge.net>
 
        PR debug/18242

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 9d01da7..2b3178c 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4264,22 +4264,8 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
       return;
     }
 
-  if (!no_new_pseudos)
-    {
-      if (GET_CODE (operands[1]) == MEM && optimize > 0
-         && (mode == QImode || mode == HImode || mode == SImode)
-         && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
-       {
-         rtx reg = gen_reg_rtx (word_mode);
-
-         emit_insn (gen_rtx_SET (word_mode, reg,
-                                 gen_rtx_ZERO_EXTEND (word_mode,
-                                                      operands[1])));
-         operands[1] = gen_lowpart (mode, reg);
-       }
-      if (GET_CODE (operands[0]) != REG)
-       operands[1] = force_reg (mode, operands[1]);
-    }
+  if (!no_new_pseudos && GET_CODE (operands[0]) != REG)
+    operands[1] = force_reg (mode, operands[1]);
 
   if (mode == SFmode && ! TARGET_POWERPC
       && TARGET_HARD_FLOAT && TARGET_FPRS

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f0678a7..296b5c6 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-02  Nathan Sidwell  <nathan@codesourcery.com>
+
+       PR rtl-optimization/17104
+       * gcc.dg/ppc-bitfield1.c: New.
+
 2004-11-01  Richard Sandiford  <rsandifo@redhat.com>
 
        * gcc.dg/uninit-H.c (ASM): Define to "$sp" on MIPS targets.

diff --git a/gcc/testsuite/gcc.dg/ppc-bitfield1.c b/gcc/testsuite/gcc.dg/ppc-bitfield1.c
new file mode 100644 (file)
index 0000000..c4b73a7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ppc-bitfield1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile { target powerpc64-*-* } } */
+/* { dg-options "-m64 -O2" } */
+
+/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31"  } } */
+/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 17104 many sign extends added.  */
+
+struct {
+ int f1 : 1;
+ int f2 : 1;
+ int f3 : 1;
+ int f4 : 1;
+ int f5 : 1;
+ int f6 : 1;
+ int f7 : 1;
+ int f8 : 1;
+ int f9 : 1;
+ int f10 : 1;
+ int f11 : 1;
+ int f12 : 1;
+ int f13 : 1;
+ int f14 : 1;
+ int f15 : 1;
+ int f16 : 1;
+ int f17 : 2;
+ int f18 : 2;
+ int f19 : 2;
+ int f20 : 2;
+ int f21 : 2;
+ int f22 : 2;
+ int f23 : 2;
+ int f24 : 2;
+ } s;
+
+void foo ()
+{
+
+    s.f1 = 0;
+    s.f2 = 0;
+    s.f3 = 0;
+    s.f4 = 0;
+    s.f5 = 0;
+    s.f6 = 0;
+    s.f7 = 0;
+    s.f8 = 0;
+    s.f9 = 0;
+    s.f10 = 0;
+    s.f11 = 0;
+    s.f12 = 0;
+    s.f13 = 0;
+    s.f14 = 0;
+    s.f15 = 0;
+    s.f16 = 0;
+    s.f17 = 0;
+    s.f18 = 0;
+    s.f19 = 0;
+    s.f20 = 0;
+    s.f21 = 0;
+    s.f22 = 0;
+    s.f23 = 0;
+    s.f24 = 0;
+
+}
+