* config/i386/constraints.md (Y0): Rename register constraint to Yz.

        (Yt): Rename register constraint to Y2.
        * config/i386/sse.md: Use renamed register constraints.
        * config/i386/mmx.md: Ditto.
        * config/i386/i386.md: Ditto.

        * config/i386/i386.md (*dummy_extendsfdf2): Fix operand 1 constraint.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@129622 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cd494ad..bff2ce2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2007-10-25  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/constraints.md (Y0): Rename register constraint to Yz.
+       (Yt): Rename register constraint to Y2.
+       * config/i386/sse.md: Use renamed register constraints.
+       * config/i386/mmx.md: Ditto.
+       * config/i386/i386.md: Ditto.
+
+2007-10-25  Rask Ingemann Lambertsen  <rask@sygehus.dk>
+
+       * config/i386/i386.md (*dummy_extendsfdf2): Fix operand 1 constraint.
+
 2007-10-24  Chao-ying Fu  <fu@mips.com>
 
        * dwarf2out.c (base_type_die): Use DW_ATE_unsigned_fixed or

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index b9bec56..134ef61 100644 (file)
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -83,15 +83,15 @@
  "Any SSE register.")
 
 ;; We use the Y prefix to denote any number of conditional register sets:
-;;  0  First SSE register.
-;;  t  SSE2 enabled
+;;  z  First SSE register.
+;;  2  SSE2 enabled
 ;;  i  SSE2 inter-unit moves enabled
 ;;  m  MMX inter-unit moves enabled
 
-(define_register_constraint "Y0" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
+(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
  "First SSE register (@code{%xmm0}).")
 
-(define_register_constraint "Yt" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
+(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
  "@internal Any SSE register, when SSE2 is enabled.")
 
 (define_register_constraint "Yi"

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c13fcbc..1681883 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2163,9 +2163,9 @@
 
 (define_insn "*movdi_2"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-                       "=r  ,o  ,*y,m*y,*y,*Yt,m  ,*Yt,*Yt,*x,m ,*x,*x")
+                       "=r  ,o  ,*y,m*y,*y,*Y2,m  ,*Y2,*Y2,*x,m ,*x,*x")
        (match_operand:DI 1 "general_operand"
-                       "riFo,riF,C ,*y ,m ,C  ,*Yt,*Yt,m  ,C ,*x,*x,m "))]
+                       "riFo,riF,C ,*y ,m ,C  ,*Y2,*Y2,m  ,C ,*x,*x,m "))]
   "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
    #
@@ -2636,7 +2636,7 @@
 
 (define_insn "*pushdf_nointeger"
   [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
-       (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Yt"))]
+       (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Y2"))]
   "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
 {
   /* This insn should be already split before reg-stack.  */
@@ -2648,7 +2648,7 @@
 
 (define_insn "*pushdf_integer"
   [(set (match_operand:DF 0 "push_operand" "=<,<,<")
-       (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Yt"))]
+       (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y2"))]
   "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
 {
   /* This insn should be already split before reg-stack.  */
@@ -2688,9 +2688,9 @@
 
 (define_insn "*movdf_nointeger"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-                       "=f,m,f,*r  ,o  ,Yt*x,Yt*x,Yt*x ,m  ")
+                       "=f,m,f,*r  ,o  ,Y2*x,Y2*x,Y2*x ,m  ")
        (match_operand:DF 1 "general_operand"
-                       "fm,f,G,*roF,F*r,C   ,Yt*x,mYt*x,Yt*x"))]
+                       "fm,f,G,*roF,F*r,C   ,Y2*x,mY2*x,Y2*x"))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
    && (reload_in_progress || reload_completed
@@ -2805,9 +2805,9 @@
 
 (define_insn "*movdf_integer_rex64"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-               "=f,m,f,r  ,m ,Yt*x,Yt*x,Yt*x,m   ,Yi,r ")
+               "=f,m,f,r  ,m ,Y2*x,Y2*x,Y2*x,m   ,Yi,r ")
        (match_operand:DF 1 "general_operand"
-               "fm,f,G,rmF,Fr,C   ,Yt*x,m   ,Yt*x,r ,Yi"))]
+               "fm,f,G,rmF,Fr,C   ,Y2*x,m   ,Y2*x,r ,Yi"))]
   "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
@@ -2926,9 +2926,9 @@
 
 (define_insn "*movdf_integer"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-               "=f,m,f,r  ,o ,Yt*x,Yt*x,Yt*x,m   ")
+               "=f,m,f,r  ,o ,Y2*x,Y2*x,Y2*x,m   ")
        (match_operand:DF 1 "general_operand"
-               "fm,f,G,roF,Fr,C   ,Yt*x,m   ,Yt*x"))]
+               "fm,f,G,roF,Fr,C   ,Y2*x,m   ,Y2*x"))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
    && (reload_in_progress || reload_completed
@@ -3564,7 +3564,7 @@
 })
 
 (define_insn "zero_extendsidi2_32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Yt")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Y2")
        (zero_extend:DI
         (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r   ,m  ,r   ,m")))
    (clobber (reg:CC FLAGS_REG))]
@@ -3581,7 +3581,7 @@
    (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")])
 
 (define_insn "zero_extendsidi2_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Yt")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Y2")
      (zero_extend:DI
        (match_operand:SI 1 "nonimmediate_operand"  "rm,0,r   ,m  ,r   ,m")))]
   "TARGET_64BIT"
@@ -3867,7 +3867,7 @@
 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
 (define_insn "*dummy_extendsfdf2"
   [(set (match_operand:DF 0 "push_operand" "=<")
-       (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
+       (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY2")))]
   "0"
   "#")
 
@@ -4172,9 +4172,9 @@
    (set_attr "mode" "SF")])
 
 (define_insn "*truncdfsf_mixed"
-  [(set (match_operand:SF 0 "nonimmediate_operand"   "=m,?fx*r,Yt")
+  [(set (match_operand:SF 0 "nonimmediate_operand"   "=m,?fx*r,Y2")
        (float_truncate:SF
-         (match_operand:DF 1 "nonimmediate_operand" "f ,f    ,Ytm")))
+         (match_operand:DF 1 "nonimmediate_operand" "f ,f    ,Y2m")))
    (clobber (match_operand:SF 2 "memory_operand"     "=X,m    ,X"))]
   "TARGET_MIX_SSE_I387"
 {
@@ -4276,7 +4276,7 @@
    (set_attr "mode" "SF")])
 
 (define_insn "*truncxfdf2_mixed"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fYt*r")
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fY2*r")
        (float_truncate:DF
          (match_operand:XF 1 "register_operand" "f,f")))
    (clobber (match_operand:DF 2 "memory_operand" "=X,m"))]
@@ -4503,7 +4503,7 @@
 
 ;; Avoid vector decoded forms of the instruction.
 (define_peephole2
-  [(match_scratch:DF 2 "Yt")
+  [(match_scratch:DF 2 "Y2")
    (set (match_operand:SSEMODEI24 0 "register_operand" "")
        (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
   "TARGET_AVOID_VECTOR_DECODE && !optimize_size"

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 7278015..ee81993 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -63,9 +63,9 @@
 
 (define_insn "*mov<mode>_internal_rex64"
   [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
-                               "=rm,r,*y,*y ,m ,*y,Yt,x,x ,m,r,x")
+                               "=rm,r,*y,*y ,m ,*y,Y2,x,x ,m,r,x")
        (match_operand:MMXMODEI 1 "vector_move_operand"
-                               "Cr ,m,C ,*ym,*y,Yt,*y,C,xm,x,x,r"))]
+                               "Cr ,m,C ,*ym,*y,Y2,*y,C,xm,x,x,r"))]
   "TARGET_64BIT && TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
@@ -87,9 +87,9 @@
 
 (define_insn "*mov<mode>_internal"
   [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
-                       "=*y,*y ,m ,*y ,*Yt,*Yt,*Yt ,m  ,*x,*x,*x,m ,?r ,?m")
+                       "=*y,*y ,m ,*y ,*Y2,*Y2,*Y2 ,m  ,*x,*x,*x,m ,?r ,?m")
        (match_operand:MMXMODEI 1 "vector_move_operand"
-                       "C  ,*ym,*y,*Yt,*y ,C  ,*Ytm,*Yt,C ,*x,m ,*x,irm,r"))]
+                       "C  ,*ym,*y,*Y2,*y ,C  ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))]
   "TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
@@ -122,9 +122,9 @@
 
 (define_insn "*movv2sf_internal_rex64"
   [(set (match_operand:V2SF 0 "nonimmediate_operand"
-                               "=rm,r,*y ,*y ,m ,*y,Yt,x,x,x,m,r,x")
+                               "=rm,r,*y ,*y ,m ,*y,Y2,x,x,x,m,r,x")
         (match_operand:V2SF 1 "vector_move_operand"
-                               "Cr ,m ,C ,*ym,*y,Yt,*y,C,x,m,x,x,r"))]
+                               "Cr ,m ,C ,*ym,*y,Y2,*y,C,x,m,x,x,r"))]
   "TARGET_64BIT && TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
@@ -147,9 +147,9 @@
 
 (define_insn "*movv2sf_internal"
   [(set (match_operand:V2SF 0 "nonimmediate_operand"
-                       "=*y,*y ,m,*y ,*Yt,*x,*x,*x,m ,?r ,?m")
+                       "=*y,*y ,m,*y ,*Y2,*x,*x,*x,m ,?r ,?m")
         (match_operand:V2SF 1 "vector_move_operand"
-                       "C ,*ym,*y,*Yt,*y ,C ,*x,m ,*x,irm,r"))]
+                       "C ,*ym,*y,*Y2,*y ,C ,*x,m ,*x,irm,r"))]
   "TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
@@ -1171,9 +1171,9 @@
 })
 
 (define_insn "*vec_extractv2si_1"
-  [(set (match_operand:SI 0 "nonimmediate_operand"     "=y,Yt,Yt,x,frxy")
+  [(set (match_operand:SI 0 "nonimmediate_operand"     "=y,Y2,Y2,x,frxy")
        (vec_select:SI
-         (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Yt,0,o")
+         (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o")
          (parallel [(const_int 1)])))]
   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6acaf93..b35ba6f 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1457,7 +1457,7 @@
 })
 
 (define_insn "vec_setv4sf_0"
-  [(set (match_operand:V4SF 0 "nonimmediate_operand"  "=x,x,Yt,m")
+  [(set (match_operand:V4SF 0 "nonimmediate_operand"  "=x,x,Y2,m")
        (vec_merge:V4SF
          (vec_duplicate:V4SF
            (match_operand:SF 2 "general_operand"     " x,m,*r,x*rfF"))
@@ -3331,10 +3331,10 @@
    (set_attr "mode" "DF")])
 
 (define_insn "*vec_concatv2df"
-  [(set (match_operand:V2DF 0 "register_operand"     "=Yt,Yt,Yt,x,x")
+  [(set (match_operand:V2DF 0 "register_operand"     "=Y2,Y2,Y2,x,x")
        (vec_concat:V2DF
          (match_operand:DF 1 "nonimmediate_operand" " 0 ,0 ,m ,0,0")
-         (match_operand:DF 2 "vector_move_operand"  " Yt,m ,C ,x,m")))]
+         (match_operand:DF 2 "vector_move_operand"  " Y2,m ,C ,x,m")))]
   "TARGET_SSE"
   "@
    unpcklpd\t{%2, %0|%0, %2}
@@ -5260,7 +5260,7 @@
   "operands[2] = CONST0_RTX (V4SImode);")
 
 (define_insn "sse2_loadld"
-  [(set (match_operand:V4SI 0 "register_operand"       "=Yt,Yi,x,x")
+  [(set (match_operand:V4SI 0 "register_operand"       "=Y2,Yi,x,x")
        (vec_merge:V4SI
          (vec_duplicate:V4SI
            (match_operand:SI 2 "nonimmediate_operand" "m  ,r ,m,x"))
@@ -5397,9 +5397,9 @@
    (set_attr "mode" "V2SF,V4SF,V2SF")])
 
 (define_insn "*vec_dupv4si"
-  [(set (match_operand:V4SI 0 "register_operand" "=Yt,x")
+  [(set (match_operand:V4SI 0 "register_operand" "=Y2,x")
        (vec_duplicate:V4SI
-         (match_operand:SI 1 "register_operand" " Yt,0")))]
+         (match_operand:SI 1 "register_operand" " Y2,0")))]
   "TARGET_SSE"
   "@
    pshufd\t{$0, %1, %0|%0, %1, 0}
@@ -5408,7 +5408,7 @@
    (set_attr "mode" "TI,V4SF")])
 
 (define_insn "*vec_dupv2di"
-  [(set (match_operand:V2DI 0 "register_operand" "=Yt,x")
+  [(set (match_operand:V2DI 0 "register_operand" "=Y2,x")
        (vec_duplicate:V2DI
          (match_operand:DI 1 "register_operand" " 0 ,0")))]
   "TARGET_SSE"
@@ -5422,10 +5422,10 @@
 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
 ;; alternatives pretty much forces the MMX alternative to be chosen.
 (define_insn "*sse2_concatv2si"
-  [(set (match_operand:V2SI 0 "register_operand"     "=Yt, Yt,*y,*y")
+  [(set (match_operand:V2SI 0 "register_operand"     "=Y2, Y2,*y,*y")
        (vec_concat:V2SI
          (match_operand:SI 1 "nonimmediate_operand" " 0 ,rm , 0,rm")
-         (match_operand:SI 2 "reg_or_0_operand"     " Yt,C  ,*y, C")))]
+         (match_operand:SI 2 "reg_or_0_operand"     " Y2,C  ,*y, C")))]
   "TARGET_SSE2"
   "@
    punpckldq\t{%2, %0|%0, %2}
@@ -5450,10 +5450,10 @@
    (set_attr "mode" "V4SF,V4SF,DI,DI")])
 
 (define_insn "*vec_concatv4si_1"
-  [(set (match_operand:V4SI 0 "register_operand"       "=Yt,x,x")
+  [(set (match_operand:V4SI 0 "register_operand"       "=Y2,x,x")
        (vec_concat:V4SI
          (match_operand:V2SI 1 "register_operand"     " 0 ,0,0")
-         (match_operand:V2SI 2 "nonimmediate_operand" " Yt,x,m")))]
+         (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,m")))]
   "TARGET_SSE"
   "@
    punpcklqdq\t{%2, %0|%0, %2}
@@ -5463,10 +5463,10 @@
    (set_attr "mode" "TI,V4SF,V2SF")])
 
 (define_insn "vec_concatv2di"
-  [(set (match_operand:V2DI 0 "register_operand"     "=Yt,?Yt,Yt,x,x,x")
+  [(set (match_operand:V2DI 0 "register_operand"     "=Y2,?Y2,Y2,x,x,x")
        (vec_concat:V2DI
          (match_operand:DI 1 "nonimmediate_operand" "  m,*y ,0 ,0,0,m")
-         (match_operand:DI 2 "vector_move_operand"  "  C,  C,Yt,x,m,0")))]
+         (match_operand:DI 2 "vector_move_operand"  "  C,  C,Y2,x,m,0")))]
   "!TARGET_64BIT && TARGET_SSE"
   "@
    movq\t{%1, %0|%0, %1}
@@ -5479,10 +5479,10 @@
    (set_attr "mode" "TI,TI,TI,V4SF,V2SF,V2SF")])
 
 (define_insn "*vec_concatv2di_rex"
-  [(set (match_operand:V2DI 0 "register_operand"     "=Yt,Yi,!Yt,Yt,x,x,x")
+  [(set (match_operand:V2DI 0 "register_operand"     "=Y2,Yi,!Y2,Y2,x,x,x")
        (vec_concat:V2DI
          (match_operand:DI 1 "nonimmediate_operand" "  m,r ,*y ,0 ,0,0,m")
-         (match_operand:DI 2 "vector_move_operand"  "  C,C ,C  ,Yt,x,m,0")))]
+         (match_operand:DI 2 "vector_move_operand"  "  C,C ,C  ,Y2,x,m,0")))]
   "TARGET_64BIT"
   "@
    movq\t{%1, %0|%0, %1}
@@ -6760,7 +6760,7 @@
   [(set (match_operand:V2DF 0 "reg_not_xmm0_operand" "=x")
        (unspec:V2DF [(match_operand:V2DF 1 "reg_not_xmm0_operand"  "0")
                      (match_operand:V2DF 2 "nonimm_not_xmm0_operand" "xm")
-                     (match_operand:V2DF 3 "register_operand" "Y0")]
+                     (match_operand:V2DF 3 "register_operand" "Yz")]
                     UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
   "blendvpd\t{%3, %2, %0|%0, %2, %3}"
@@ -6772,7 +6772,7 @@
   [(set (match_operand:V4SF 0 "reg_not_xmm0_operand" "=x")
        (unspec:V4SF [(match_operand:V4SF 1 "reg_not_xmm0_operand" "0")
                      (match_operand:V4SF 2 "nonimm_not_xmm0_operand" "xm")
-                     (match_operand:V4SF 3 "register_operand" "Y0")]
+                     (match_operand:V4SF 3 "register_operand" "Yz")]
                     UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
   "blendvps\t{%3, %2, %0|%0, %2, %3}"
@@ -6843,7 +6843,7 @@
   [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
        (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand"  "0")
                       (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
-                      (match_operand:V16QI 3 "register_operand" "Y0")]
+                      (match_operand:V16QI 3 "register_operand" "Yz")]
                      UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
   "pblendvb\t{%3, %2, %0|%0, %2, %3}"
@@ -7315,7 +7315,7 @@
           (match_operand:SI 5 "register_operand" "d,d")
           (match_operand:SI 6 "const_0_to_255_operand" "n,n")]
          UNSPEC_PCMPESTR))
-   (set (match_operand:V16QI 1 "register_operand" "=Y0,Y0")
+   (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
        (unspec:V16QI
          [(match_dup 2)
           (match_dup 3)
@@ -7387,7 +7387,7 @@
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_2_pcmpestrm"
-  [(set (match_operand:V16QI 0 "register_operand" "=Y0,Y0")
+  [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
        (unspec:V16QI
          [(match_operand:V16QI 1 "register_operand" "x,x")
           (match_operand:SI 2 "register_operand" "a,a")
@@ -7420,7 +7420,7 @@
           (match_operand:SI 3 "register_operand" "d,d,d,d")
           (match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
          UNSPEC_PCMPESTR))
-   (clobber (match_scratch:V16QI 5 "=Y0,Y0,X,X"))
+   (clobber (match_scratch:V16QI 5 "=Yz,Yz,X,X"))
    (clobber (match_scratch:SI    6 "= X, X,c,c"))]
   "TARGET_SSE4_2"
   "@
@@ -7441,7 +7441,7 @@
           (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
           (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
          UNSPEC_PCMPISTR))
-   (set (match_operand:V16QI 1 "register_operand" "=Y0,Y0")
+   (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
        (unspec:V16QI
          [(match_dup 2)
           (match_dup 3)
@@ -7502,7 +7502,7 @@
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_2_pcmpistrm"
-  [(set (match_operand:V16QI 0 "register_operand" "=Y0,Y0")
+  [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
        (unspec:V16QI
          [(match_operand:V16QI 1 "register_operand" "x,x")
           (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
@@ -7529,7 +7529,7 @@
           (match_operand:V16QI 1 "nonimmediate_operand" "x,m,x,m")
           (match_operand:SI 2 "const_0_to_255_operand" "n,n,n,n")]
          UNSPEC_PCMPISTR))
-   (clobber (match_scratch:V16QI 3 "=Y0,Y0,X,X"))
+   (clobber (match_scratch:V16QI 3 "=Yz,Yz,X,X"))
    (clobber (match_scratch:SI    4 "= X, X,c,c"))]
   "TARGET_SSE4_2"
   "@