* config/h8300/h8300.md: Remove bit extraction patterns that

	cannot be triggered.
	Restrict each bit extraction pattern to a variant on which the
	pattern is tested.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@49253 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 147a32d..24dd82c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2002-01-26  Kazu Hirata  <kazu@hxi.com>
+
+       * config/h8300/h8300.md: Remove bit extraction patterns that
+       cannot be triggered.
+       Restrict each bit extraction pattern to a variant on which the
+       pattern is tested.
+
 2002-01-26  Joseph S. Myers  <jsm28@cam.ac.uk>
 
        * doc/include/texinfo.tex: Update to version 2002-01-04.07.

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 27cb07c..f94778b 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1973,25 +1973,13 @@
 ;;
 ;; Normal loads with a 16bit destination.
 ;;
-;; Yes, both cases are needed.
-;;
+
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=&r")
        (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
                         (const_int 1)
                         (match_operand:HI 2 "immediate_operand" "n")))]
-  ""
-  "sub.w       %0,%0\;bld      %Z2,%Y1\;bst    #0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-       (subreg:HI (zero_extract:SI
-                    (match_operand:HI 1 "register_operand" "r")
-                    (const_int 1)
-                    (match_operand:HI 2 "immediate_operand" "n")) 2))]
-  ""
+  "TARGET_H8300"
   "sub.w       %0,%0\;bld      %Z2,%Y1\;bst    #0,%X0"
   [(set_attr "cc" "clobber")
    (set_attr "length" "6")])
@@ -1999,8 +1987,6 @@
 ;;
 ;; Inverted loads with a 16bit destination.
 ;;
-;; Yes, all four cases are needed.
-;;
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=&r")
@@ -2008,46 +1994,8 @@
                                 (match_operand:HI 3 "p_operand" "P"))
                         (const_int 1)
                         (match_operand:HI 2 "const_int_operand" "n")))]
-  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
-  "sub.w       %0,%0\;bild     %Z2,%Y1\;bst    #0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-       (and:HI (not:HI
-                 (lshiftrt:HI
-                   (match_operand:HI 1 "bit_operand" "Ur")
-                   (match_operand:HI 2 "const_int_operand" "n")))
-               (const_int 1)))]
-  ""
-  "sub.w       %0,%0\;bild     %Z2,%Y1\;bst    #0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-       (and:HI (not:HI
-                 (subreg:HI
-                   (lshiftrt:SI
-                     (match_operand:SI 1 "register_operand" "Ur")
-                     (match_operand:SI 2 "const_int_operand" "n")) 2))
-               (const_int 1)))]
-  "INTVAL (operands[2]) < 16"
-  "sub.w       %0,%0\;bild     %Z2,%Y1\;bst    #0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-       (and:HI (not:HI
-                 (subreg:HI
-                   (lshiftrt:SI
-                     (match_operand:SI 1 "bit_operand" "Ur")
-                     (match_operand:SI 2 "const_int_operand" "n")) 0))
-               (const_int 1)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-   && INTVAL (operands[2]) < 16"
+  "TARGET_H8300
+   && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
   "sub.w       %0,%0\;bild     %Z2,%Y1\;bst    #0,%X0"
   [(set_attr "cc" "clobber")
    (set_attr "length" "8")])