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(probe+2, probe+4): New conditional move patterns.
authorwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 10 Feb 1996 00:05:30 +0000 (00:05 +0000)
committerwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 10 Feb 1996 00:05:30 +0000 (00:05 +0000)
(movsicc): Don't truncate comparison if it is DImode.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@11191 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/config/mips/mips.md

index 23e35a3..ead8cdc 100644 (file)
@@ -6480,6 +6480,21 @@ move\\t%0,%z4\\n\\
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
        (if_then_else:SI
+        (match_operator 4 "equality_op"
+                        [(match_operand:DI 1 "register_operand" "d,d")
+                         (const_int 0)])
+        (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
+        (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4"
+  "@
+    mov%B4\\t%0,%z2,%1
+    mov%b4\\t%0,%z3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SI")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+       (if_then_else:SI
         (match_operator 3 "equality_op" [(reg:CC_FP 67) (const_int 0)])
         (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
         (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
@@ -6494,6 +6509,21 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "=d,d")
        (if_then_else:DI
         (match_operator 4 "equality_op"
+                        [(match_operand:SI 1 "register_operand" "d,d")
+                         (const_int 0)])
+        (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
+        (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4"
+  "@
+    mov%B4\\t%0,%z2,%1
+    mov%b4\\t%0,%z3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DI")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+       (if_then_else:DI
+        (match_operator 4 "equality_op"
                         [(match_operand:DI 1 "register_operand" "d,d")
                          (const_int 0)])
         (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
@@ -6661,13 +6691,8 @@ move\\t%0,%z4\\n\\
       operands[4] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
     }
 
-  if (mode == DImode)
-    operands[5] = gen_rtx (move_code, VOIDmode,
-                          gen_lowpart (SImode, operands[4]),
-                          CONST0_RTX (SImode));
-  else
-    operands[5] = gen_rtx (move_code, VOIDmode, operands[4],
-                          CONST0_RTX (SImode));
+  operands[5] = gen_rtx (move_code, VOIDmode, operands[4],
+                        CONST0_RTX (SImode));
 }")
 
 ;; ??? Need movdicc, movsfcc, and movdfcc patterns.  They should be