* config/h8300/h8300.c (fix_bit_operand): Don't generate insns

	by hand.
	* config/h8300/h8300.md (*andqi3_1): Change to andqi3_1.
	(*iorqi3_1): Change to iorqi3_1.
	(*xorqi3_1): Change to xorqi3_1.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@77997 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3dd2ff8..42612f0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,13 @@
 2004-02-17  Kazu Hirata  <kazu@cs.umass.edu>
 
+       * config/h8300/h8300.c (fix_bit_operand): Don't generate insns
+       by hand.
+       * config/h8300/h8300.md (*andqi3_1): Change to andqi3_1.
+       (*iorqi3_1): Change to iorqi3_1.
+       (*xorqi3_1): Change to xorqi3_1.
+
+2004-02-17  Kazu Hirata  <kazu@cs.umass.edu>
+
        * c-common.c, cfghooks.c, rtlanal.c, varasm.c: Fix comment
        typos.
 

diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index a06f87c..894c3aa 100644 (file)
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -4109,10 +4109,21 @@ fix_bit_operand (rtx *operands, int what, enum rtx_code type)
   operands[1] = force_reg (QImode, operands[1]);
   {
     rtx res = gen_reg_rtx (QImode);
-    emit_insn (gen_rtx_SET (VOIDmode, res,
-                           gen_rtx_fmt_ee (type, QImode,
-                                           operands[1], operands[2])));
-    emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
+    switch (type)
+      {
+      case AND:
+       emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
+       break;
+      case IOR:
+       emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
+       break;
+      case XOR:
+       emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
+       break;
+      default:
+       abort ();
+      }
+    emit_insn (gen_movqi (operands[0], res));
   }
   return 1;
 }

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 8671e1f..f18f007 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1183,7 +1183,7 @@
 ;; AND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*andqi3_1"
+(define_insn "andqi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
        (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
@@ -1279,7 +1279,7 @@
 ;; OR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*iorqi3_1"
+(define_insn "iorqi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
        (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
@@ -1320,7 +1320,7 @@
 ;; XOR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*xorqi3_1"
+(define_insn "xorqi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
        (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "rn,n")))]