{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %L0\", operands);
- else if (zero_areg)
+ else if (zero_areg
+ && (REGNO_REG_CLASS (REGNO (operands[0]))
+ == ADDRESS_REGS))
{
rtx xoperands[2];
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %H0\", operands);
- else if (zero_areg)
+ else if (zero_areg
+ && (REGNO_REG_CLASS (REGNO (operands[0]))
+ == ADDRESS_REGS))
{
rtx xoperands[2];
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %L0\", operands);
- else if (zero_areg)
+ else if (zero_areg
+ && (REGNO_REG_CLASS (REGNO (operands[0]))
+ == ADDRESS_REGS))
{
rtx xoperands[2];
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
output_asm_insn (\"clr %H0\", operands);
- else if (zero_areg)
+ else if (zero_areg
+ && (REGNO_REG_CLASS (REGNO (operands[0]))
+ == ADDRESS_REGS))
{
rtx xoperands[2];
;; AND INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "andsi3"
+(define_expand "andsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (and:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx,dx")
(and:SI (match_operand:SI 1 "register_operand" "%0,0")
(match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "iorsi3"
+(define_expand "iorsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ior:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(ior:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "nonmemory_operand" "dxi")))]
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "xorsi3"
+(define_expand "xorsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (xor:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(xor:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "nonmemory_operand" "dxi")))]
;; NOT INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "one_cmplsi2"
+(define_expand "one_cmplsi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (not:SI (match_operand:SI 1 "register_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(not:SI (match_operand:SI 1 "register_operand" "0")))]
""
;; EXTEND INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "zero_extendqisi2"
+(define_expand "zero_extendqisi2"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extend:SI
+ (match_operand:QI 1 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
(zero_extend:SI
(match_operand:QI 1 "general_operand" "0,d,m")))]
movbu %1,%0"
[(set_attr "cc" "none_0hit")])
-(define_insn "zero_extendhisi2"
+(define_expand "zero_extendhisi2"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (zero_extend:SI
+ (match_operand:HI 1 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
(zero_extend:SI
(match_operand:HI 1 "general_operand" "0,dx,m")))]
;;- sign extension instructions
-(define_insn "extendqisi2"
+(define_expand "extendqisi2"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (sign_extend:SI
+ (match_operand:QI 1 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx")
(sign_extend:SI
(match_operand:QI 1 "general_operand" "0,dx")))]
mov %1,%0\;extb %0"
[(set_attr "cc" "none_0hit")])
-(define_insn "extendhisi2"
+(define_expand "extendhisi2"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (sign_extend:SI
+ (match_operand:HI 1 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx")
(sign_extend:SI
(match_operand:HI 1 "general_operand" "0,dx")))]
;; SHIFTS
;; ----------------------------------------------------------------------
-(define_insn "ashlsi3"
+(define_expand "ashlsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ashift:SI
+ (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
(ashift:SI
(match_operand:SI 1 "register_operand" "0,0,0,0,0")
asl %S2,%0"
[(set_attr "cc" "set_zn")])
-(define_insn "lshrsi3"
+(define_expand "lshrsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (lshiftrt:SI
+ (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(lshiftrt:SI
(match_operand:SI 1 "register_operand" "0")
"lsr %S2,%0"
[(set_attr "cc" "set_zn")])
-(define_insn "ashrsi3"
+(define_expand "ashrsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ashiftrt:SI
+ (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(ashiftrt:SI
(match_operand:SI 1 "register_operand" "0")