+2004-02-01 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/h8300/h8300.md (two peephole2's): New.
+
2004-02-01 Eric Botcazou <ebotcazou@libertysurf.fr>
* config/sparc/sol2-bi.h: Handle TARGET_CPU_ultrasparc3.
"operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
+
+;; These triggers right at the end of allocation of locals in the
+;; prologue. The only profitable cases are when we have stack
+;; adjustment of -4 or -12. That of -8 won't happen because it is
+;; always split into two consecutive subtractions of -4.
+
+(define_peephole2
+ [(set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (const_int -4)))
+ (set (mem:SI (reg:SI SP_REG))
+ (match_operand:SI 0 "register_operand" ""))]
+ "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
+ && REGNO (operands[0]) != SP_REG"
+ [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+ (match_dup 0))]
+ "")
+
+(define_peephole2
+ [(set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (const_int -12)))
+ (set (mem:SI (reg:SI SP_REG))
+ (match_operand:SI 0 "register_operand" ""))]
+ "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
+ && REGNO (operands[0]) != SP_REG"
+ [(set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (const_int -4)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (const_int -4)))
+ (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
+ (match_dup 0))]
+ "")