(divsi3): Correct logic for when we call force_reg.

(modsi3): Ensure operands[2] is a CONST_INT; include REG in predicate.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@6248 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bd8fc6b..72957ae 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -754,17 +754,16 @@
   if (GET_CODE (operands[2]) == CONST_INT
       && exact_log2 (INTVAL (operands[2])) >= 0)
     ;
-
   else if (! TARGET_POWERPC)
     FAIL;
-
-  operands[2] = force_reg (SImode, operands[2]);
+  else
+    operands[2] = force_reg (SImode, operands[2]);
 }")
 
 (define_expand "modsi3"
   [(use (match_operand:SI 0 "gpc_reg_operand" ""))
    (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "const_int_operand" ""))]
+   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
   ""
   "
 {
@@ -772,7 +771,7 @@
   rtx temp1;
   rtx temp2;
 
-  if (i < 0)
+  if (GET_CODE (operands[2]) != CONST_INT || i < 0)
     FAIL;
 
   temp1 = gen_reg_rtx (SImode);