(movqi): Enable use of clr and st insns on TARGET_5200.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@13576 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index c242f42..83d3879 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -993,12 +993,13 @@
   /* clr and st insns on 68000 read before writing.
      This isn't so on the 68010, but we have no TARGET_68010.  */
   if (!ADDRESS_REG_P (operands[0])
-      && (TARGET_68020
+      && ((TARGET_68020 || TARGET_5200)
          || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
     {
       if (operands[1] == const0_rtx)
        return \"clr%.b %0\";
-      if (GET_CODE (operands[1]) == CONST_INT
+      if ((!TARGET_5200 || DATA_REG_P (operands[0]))
+          && GET_CODE (operands[1]) == CONST_INT
          && (INTVAL (operands[1]) & 255) == 255)
        {
          CC_STATUS_INIT;
@@ -4356,13 +4357,13 @@
   "!TARGET_5200"
   "lsl%.b %1,%0")
 
-;; On all 68k models, this makes faster code in a special case.
+;; On most 68k models, this makes faster code in a special case.
 
 (define_insn "ashrsi_16"
   [(set (match_operand:SI 0 "register_operand" "=d")
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
                     (const_int 16)))]
-  ""
+  "!TARGET_68060"
   "swap %0\;ext%.l %0")
 
 ;; On the 68000, this makes faster code in a special case.