PR rtl-optimization/54739

	* config/pa/pa.md: Remove DImode and, not and, ior and xor patterns
	for 32-bit targets.  Adjust expanders.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192152 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2261ec4..6178f33 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2012-10-05  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
+       PR rtl-optimization/54739
+       * config/pa/pa.md: Remove DImode and, not and, ior and xor patterns
+       for 32-bit targets.  Adjust expanders.
+
        * config/pa/pa.md: Adjust unamed HImode add insn pattern.
 
 2012-10-05  Oleg Endo  <olegendo@gcc.gnu.org>

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 4595357..80c40f5 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5623,22 +5623,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
        (and:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "and_operand" "")))]
-  ""
-  "
-{
-  /* Both operands must be register operands.  */
-  if (!TARGET_64BIT && !register_operand (operands[2], DImode))
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (and:DI (match_operand:DI 1 "register_operand" "%r")
-               (match_operand:DI 2 "register_operand" "r")))]
-  "!TARGET_64BIT"
-  "and %1,%2,%0\;and %R1,%R2,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
+  "TARGET_64BIT"
+  "")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -5664,15 +5650,6 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
                (match_operand:DI 2 "register_operand" "r")))]
-  "!TARGET_64BIT"
-  "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
-               (match_operand:DI 2 "register_operand" "r")))]
   "TARGET_64BIT"
   "andcm %2,%1,%0"
   [(set_attr "type" "binary")
@@ -5691,22 +5668,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
        (ior:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
-  ""
-  "
-{
-  /* Both operands must be register operands.  */
-  if (!TARGET_64BIT && !register_operand (operands[2], DImode))
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (ior:DI (match_operand:DI 1 "register_operand" "%r")
-               (match_operand:DI 2 "register_operand" "r")))]
-  "!TARGET_64BIT"
-  "or %1,%2,%0\;or %R1,%R2,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
+  "TARGET_64BIT"
+  "")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -5756,19 +5719,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
        (xor:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "register_operand" "")))]
-  ""
-  "
-{
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (xor:DI (match_operand:DI 1 "register_operand" "%r")
-               (match_operand:DI 2 "register_operand" "r")))]
-  "!TARGET_64BIT"
-  "xor %1,%2,%0\;xor %R1,%R2,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
+  "TARGET_64BIT"
+  "")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")