+2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+ Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
+
+ * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH.
+ * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with
+ UNITS_PER_LONG where it is ABI relevant.
+ (s390_return_addr_rtx): Likewise.
+ (s390_back_chain_rtx): Likewise.
+ (s390_frame_area): Likewise.
+ (s390_frame_info): Likewise.
+ (s390_initial_elimination_offset): Likewise.
+ (save_gprs): Likewise.
+ (s390_emit_prologue): Likewise.
+ (s390_emit_epilogue): Likewise.
+ (s390_function_arg_advance): Likewise.
+ (s390_function_arg): Likewise.
+ (s390_va_start): Likewise.
+ (s390_gimplify_va_arg): Likewise.
+ (s390_function_profiler): Likewise.
+ (s390_optimize_prologue): Likewise.
+ (s390_rtx_costs): Likewise.
+ (s390_secondary_reload): Likewise.
+ (s390_promote_function_mode): Likewise.
+ (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH.
+ (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit
+ registers available.
+ (s390_unwind_word_mode): New function.
+ (s390_function_value): Split 64 bit values into register pair if
+ used as return value.
+ (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for
+ function call parameters. Handle parallels.
+ (TARGET_SCALAR_MODE_SUPPORTED_P): New macro.
+ (HARD_REGNO_CALL_PART_CLOBBERED): New macro.
+ (DWARF_CIE_DATA_ALIGNMENT): New macro.
+ (s390_expand_setmem): Remove unused variable src_addr.
+ * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to
+ deal with 64 bit registers.
+ * gcc/config/s390/s390.h: Define __zarch__ predefined macro.
+ Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant.
+ (UNITS_PER_LONG): New macro.
+ * libjava/include/s390-signal.h: Define extended ucontext
+ structure containing the upper halfs of the 64 bit registers.
+
2010-04-13 Simon Baldwin <simonb@google.com>
* cfgexpand.c (gimple_expand_cfg): Clarify warning message text.
if (REG_P (parm_rtx))
{
- for (reg = 0;
- reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
- reg++)
+ int n_regs;
+
+ /* Only integer registers (r6) are call saved and used for
+ parameter passing. */
+ if (REGNO_REG_CLASS (REGNO (parm_rtx)) == FP_REGS)
+ continue;
+
+ n_regs = ((GET_MODE_SIZE (GET_MODE (parm_rtx)) + UNITS_PER_LONG - 1)
+ / UNITS_PER_LONG);
+
+ for (reg = 0; reg < n_regs; reg++)
if (!call_used_regs[reg + REGNO (parm_rtx)])
return true;
}
if (GET_CODE (parm_rtx) == PARALLEL)
{
int i;
-
for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
{
rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
+ int n_regs;
gcc_assert (REG_P (r));
- for (reg = 0;
- reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
- reg++)
+ /* Only integer registers (r6) are call saved and used
+ for parameter passing. */
+ if (REGNO_REG_CLASS (REGNO (r)) == FP_REGS)
+ continue;
+
+ n_regs = ((GET_MODE_SIZE (GET_MODE (r)) + UNITS_PER_LONG - 1)
+ / UNITS_PER_LONG);
+
+ for (reg = 0; reg < n_regs; reg++)
if (!call_used_regs[reg + REGNO (r)])
return true;
}