2002-05-15 Aldy Hernandez <aldyh@redhat.com>

        * config/rs6000/rs6000.md ("altivec_mtvscr"): Set VSCR register.
        ("altivec_mfvscr"): Read from VSCR.

        Add vscr sets for the following insns: altivec_vctuxs,
        altivec_vaddubs, altivec_vaddsbs, altivec_vadduhs,
        altivec_vaddshs, altivec_vadduws, altivec_vaddsws, altivec_vctsxs,
        altivec_vmhaddshs, altivec_vmhraddshs, altivec_vmsumuhs,
        altivec_vmsumshs, altivec_vpkuhss, altivec_vpkshss,
        altivec_vpkuwss, altivec_vpkswss, altivec_vpkuhus,
        altivec_vpkshus, altivec_vpkuwus, altivec_vpkswus,
        altivec_vsububs, altivec_vsubsbs, altivec_vsubuhs,
        altivec_vsubshs, altivec_vsubuws, altivec_vsubsws,
        altivec_vsum4ubs, altivec_vsum4sbs, altivec_vsum4shs,
        altivec_vsum2sws, altivec_vsumsws.

        * config/rs6000/rs6000.h: Add VSCR fixed register.
        (CALL_REALLY_USED_REGISTERS): Add vscr.
        (CALL_USED_REGISTERS): Same.
        (FIXED_REGISTERS): Same.
        (REG_ALLOC_ORDER): Same.
        (reg_class): Add VSCR_REGS.
        (REG_CLASS_NAMES): Same.
        (REG_CLASS_CONTENTS): Same.
        (VSCR_REGNO): New.
        (REGISTER_NAMES): Add vscr.
        (DEBUG_REGISTER_NAMES): Same.
        (ADDITIONAL_REGISTER_NAMES): Same.
        (FIRST_PSEUDO_REGISTER): Increment.
        (CONDITIONAL_REGISTER_USAGE): Set VSCR as a global register.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@53495 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 14caa87..0d3f409 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,35 @@
+2002-05-15  Aldy Hernandez  <aldyh@redhat.com>
+
+        * config/rs6000/rs6000.md ("altivec_mtvscr"): Set VSCR register.
+        ("altivec_mfvscr"): Read from VSCR.
+
+        Add vscr sets for the following insns: altivec_vctuxs,
+        altivec_vaddubs, altivec_vaddsbs, altivec_vadduhs,
+        altivec_vaddshs, altivec_vadduws, altivec_vaddsws, altivec_vctsxs,
+        altivec_vmhaddshs, altivec_vmhraddshs, altivec_vmsumuhs,
+        altivec_vmsumshs, altivec_vpkuhss, altivec_vpkshss,
+        altivec_vpkuwss, altivec_vpkswss, altivec_vpkuhus,
+        altivec_vpkshus, altivec_vpkuwus, altivec_vpkswus,
+        altivec_vsububs, altivec_vsubsbs, altivec_vsubuhs,
+        altivec_vsubshs, altivec_vsubuws, altivec_vsubsws,
+        altivec_vsum4ubs, altivec_vsum4sbs, altivec_vsum4shs,
+        altivec_vsum2sws, altivec_vsumsws.
+
+        * config/rs6000/rs6000.h: Add VSCR fixed register.
+        (CALL_REALLY_USED_REGISTERS): Add vscr.
+        (CALL_USED_REGISTERS): Same.
+        (FIXED_REGISTERS): Same.
+        (REG_ALLOC_ORDER): Same.
+        (reg_class): Add VSCR_REGS.
+        (REG_CLASS_NAMES): Same.
+        (REG_CLASS_CONTENTS): Same.
+        (VSCR_REGNO): New.
+        (REGISTER_NAMES): Add vscr.
+        (DEBUG_REGISTER_NAMES): Same.
+        (ADDITIONAL_REGISTER_NAMES): Same.
+        (FIRST_PSEUDO_REGISTER): Increment.
+        (CONDITIONAL_REGISTER_USAGE): Set VSCR as a global register.
+
 2002-05-15  Jakub Jelinek  <jakub@redhat.com>
 
        * fold-const.c (fold): Fix a typo.

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 91627a2..fa47a97 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -683,7 +683,7 @@ extern int rs6000_default_long_calls;
    a register, in order to work around problems in allocating stack storage
    in inline functions.  */
 
-#define FIRST_PSEUDO_REGISTER 110
+#define FIRST_PSEUDO_REGISTER 111
 
 /* This must be included for pre gcc 3.0 glibc compatibility.  */
 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
@@ -707,7 +707,7 @@ extern int rs6000_default_long_calls;
    /* AltiVec registers.  */                      \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   1                                              \
+   1, 1                                                   \
 }
 
 /* 1 for registers not available across function calls.
@@ -726,7 +726,7 @@ extern int rs6000_default_long_calls;
    /* AltiVec registers.  */                      \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   1                                              \
+   1, 1                                                   \
 }
 
 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -744,7 +744,7 @@ extern int rs6000_default_long_calls;
    /* AltiVec registers.  */                      \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   0                                              \
+   0, 0                                                   \
 }
 
 #define MQ_REGNO     64
@@ -759,6 +759,7 @@ extern int rs6000_default_long_calls;
 #define LAST_ALTIVEC_REGNO     108
 #define TOTAL_ALTIVEC_REGS     (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
 #define VRSAVE_REGNO           109
+#define VSCR_REGNO             110
 
 /* List the order in which to allocate registers.  Each register must be
    listed once, even those in FIXED_REGISTERS.
@@ -781,7 +782,7 @@ extern int rs6000_default_long_calls;
        mq              (not saved; best to use it if we can)
        ctr             (not saved; when we have the choice ctr is better)
        lr              (saved)
-        cr5, r1, r2, ap, xer, vrsave (fixed)
+        cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
 
        AltiVec registers:
        v0 - v1         (not saved or used for anything)
@@ -812,7 +813,7 @@ extern int rs6000_default_long_calls;
    79,                                                 \
    96, 95, 94, 93, 92, 91,                             \
    108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98,        \
-   97, 109                                             \
+   97, 109, 110                                                \
 }
 
 /* True if register is floating-point.  */
@@ -967,6 +968,8 @@ extern int rs6000_default_long_calls;
       = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]                     \
       = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]                 \
       = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;     \
+  if (TARGET_ALTIVEC)                                                   \
+    global_regs[VSCR_REGNO] = 1;                                        \
   if (! TARGET_ALTIVEC)                                                        \
     {                                                                  \
       for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)      \
@@ -1051,6 +1054,7 @@ enum reg_class
   FLOAT_REGS,
   ALTIVEC_REGS,
   VRSAVE_REGS,
+  VSCR_REGS,
   NON_SPECIAL_REGS,
   MQ_REGS,
   LINK_REGS,
@@ -1078,6 +1082,7 @@ enum reg_class
   "FLOAT_REGS",                                                                \
   "ALTIVEC_REGS",                                                      \
   "VRSAVE_REGS",                                                       \
+  "VSCR_REGS",                                                         \
   "NON_SPECIAL_REGS",                                                  \
   "MQ_REGS",                                                           \
   "LINK_REGS",                                                         \
@@ -1104,6 +1109,7 @@ enum reg_class
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */       \
   { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */     \
   { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */             \
+  { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */       \
   { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
   { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */         \
   { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */       \
@@ -1136,6 +1142,7 @@ enum reg_class
   : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS  \
   : (REGNO) == XER_REGNO ? XER_REGS            \
   : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS      \
+  : (REGNO) == VSCR_REGNO ? VRSAVE_REGS        \
   : NO_REGS)
 
 /* The class value for index registers, and the one for base regs.  */
@@ -2626,6 +2633,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   &rs6000_reg_names[107][0],   /* v30  */                              \
   &rs6000_reg_names[108][0],   /* v31  */                              \
   &rs6000_reg_names[109][0],   /* vrsave  */                           \
+  &rs6000_reg_names[110][0],   /* vscr  */                             \
 }
 
 /* print-rtl can't handle the above REGISTER_NAMES, so define the
@@ -2649,7 +2657,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
      "v8",  "v9", "v10", "v11", "v12", "v13", "v14", "v15",             \
     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",             \
     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",             \
-    "vrsave"                                                           \
+    "vrsave", "vscr"                                                   \
 }
 
 /* Table of additional register names to use in user input.  */
@@ -2679,7 +2687,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"v20",  97}, {"v21",  98}, {"v22",  99}, {"v23",  100},     \
   {"v24",  101},{"v25",  102},{"v26",  103},{"v27",  104},      \
   {"v28",  105},{"v29",  106},{"v30",  107},{"v31",  108},      \
-  {"vrsave", 109},                                             \
+  {"vrsave", 109}, {"vscr", 110},                              \
   /* no additional names for: mq, lr, ctr, ap */               \
   {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71},      \
   {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75},      \

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 423ecfd..793d21f 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14166,7 +14166,8 @@
 (define_insn "altivec_vaddubs"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-                       (match_operand:V16QI 2 "register_operand" "v")] 36))]
+                       (match_operand:V16QI 2 "register_operand" "v")] 36))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vaddubs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -14174,7 +14175,8 @@
 (define_insn "altivec_vaddsbs"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-                       (match_operand:V16QI 2 "register_operand" "v")] 37))]
+                       (match_operand:V16QI 2 "register_operand" "v")] 37))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vaddsbs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -14182,7 +14184,8 @@
 (define_insn "altivec_vadduhs"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-                      (match_operand:V8HI 2 "register_operand" "v")] 38))]
+                      (match_operand:V8HI 2 "register_operand" "v")] 38))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vadduhs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -14190,7 +14193,8 @@
 (define_insn "altivec_vaddshs"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-                      (match_operand:V8HI 2 "register_operand" "v")] 39))]
+                      (match_operand:V8HI 2 "register_operand" "v")] 39))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vaddshs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -14198,7 +14202,8 @@
 (define_insn "altivec_vadduws"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 40))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 40))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vadduws %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -14206,7 +14211,8 @@
 (define_insn "altivec_vaddsws"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 41))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 41))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vaddsws %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -14453,7 +14459,8 @@
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                      (match_operand:V8HI 2 "register_operand" "v")
-                      (match_operand:V4SI 3 "register_operand" "v")] 69))]
+                      (match_operand:V4SI 3 "register_operand" "v")] 69))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vmsumuhs %0, %1, %2, %3"
   [(set_attr "type" "veccomplex")])
@@ -14462,7 +14469,8 @@
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                      (match_operand:V8HI 2 "register_operand" "v")
-                      (match_operand:V4SI 3 "register_operand" "v")] 70))]
+                      (match_operand:V4SI 3 "register_operand" "v")] 70))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vmsumshs %0, %1, %2, %3"
   [(set_attr "type" "veccomplex")])
@@ -14527,7 +14535,8 @@
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                      (match_operand:V8HI 2 "register_operand" "v")
-                      (match_operand:V8HI 3 "register_operand" "v")] 71))]
+                      (match_operand:V8HI 3 "register_operand" "v")] 71))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vmhaddshs %0, %1, %2, %3"
   [(set_attr "type" "veccomplex")])
@@ -14535,7 +14544,8 @@
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                      (match_operand:V8HI 2 "register_operand" "v")
-                      (match_operand:V8HI 3 "register_operand" "v")] 72))]
+                      (match_operand:V8HI 3 "register_operand" "v")] 72))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vmhraddshs %0, %1, %2, %3"
   [(set_attr "type" "veccomplex")])
@@ -14822,7 +14832,8 @@
 (define_insn "altivec_vpkuhss"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-                       (match_operand:V8HI 2 "register_operand" "v")] 96))]
+                       (match_operand:V8HI 2 "register_operand" "v")] 96))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkuhss %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14830,7 +14841,8 @@
 (define_insn "altivec_vpkshss"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-                       (match_operand:V8HI 2 "register_operand" "v")] 97))]
+                       (match_operand:V8HI 2 "register_operand" "v")] 97))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkshss %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14838,7 +14850,8 @@
 (define_insn "altivec_vpkuwss"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 98))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 98))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkuwss %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14846,7 +14859,8 @@
 (define_insn "altivec_vpkswss"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 99))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 99))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkswss %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14854,7 +14868,8 @@
 (define_insn "altivec_vpkuhus"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-                       (match_operand:V8HI 2 "register_operand" "v")] 100))]
+                       (match_operand:V8HI 2 "register_operand" "v")] 100))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkuhus %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14862,7 +14877,8 @@
 (define_insn "altivec_vpkshus"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-                       (match_operand:V8HI 2 "register_operand" "v")] 101))]
+                       (match_operand:V8HI 2 "register_operand" "v")] 101))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkshus %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14870,7 +14886,8 @@
 (define_insn "altivec_vpkuwus"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 102))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 102))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkuwus %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -14878,7 +14895,8 @@
 (define_insn "altivec_vpkswus"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 103))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 103))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vpkswus %0,%1,%2"
   [(set_attr "type" "vecperm")])
@@ -15054,7 +15072,8 @@
 (define_insn "altivec_vsububs"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-                       (match_operand:V16QI 2 "register_operand" "v")] 125))]
+                       (match_operand:V16QI 2 "register_operand" "v")] 125))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsububs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -15062,7 +15081,8 @@
 (define_insn "altivec_vsubsbs"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
-                       (match_operand:V16QI 2 "register_operand" "v")] 126))]
+                       (match_operand:V16QI 2 "register_operand" "v")] 126))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsubsbs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -15070,7 +15090,8 @@
 (define_insn "altivec_vsubuhs"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-                      (match_operand:V8HI 2 "register_operand" "v")] 127))]
+                      (match_operand:V8HI 2 "register_operand" "v")] 127))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsubuhs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -15078,7 +15099,8 @@
 (define_insn "altivec_vsubshs"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
-                      (match_operand:V8HI 2 "register_operand" "v")] 128))]
+                      (match_operand:V8HI 2 "register_operand" "v")] 128))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsubshs %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -15086,7 +15108,8 @@
 (define_insn "altivec_vsubuws"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 129))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 129))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsubuws %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -15094,7 +15117,8 @@
 (define_insn "altivec_vsubsws"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 130))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 130))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsubsws %0,%1,%2"
   [(set_attr "type" "vecsimple")])
@@ -15102,7 +15126,8 @@
 (define_insn "altivec_vsum4ubs"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 131))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 131))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsum4ubs %0,%1,%2"
   [(set_attr "type" "veccomplex")])
@@ -15110,7 +15135,8 @@
 (define_insn "altivec_vsum4sbs"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 132))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 132))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsum4sbs %0,%1,%2"
   [(set_attr "type" "veccomplex")])
@@ -15118,7 +15144,8 @@
 (define_insn "altivec_vsum4shs"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 133))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 133))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsum4shs %0,%1,%2"
   [(set_attr "type" "veccomplex")])
@@ -15126,7 +15153,8 @@
 (define_insn "altivec_vsum2sws"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 134))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 134))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsum2sws %0,%1,%2"
   [(set_attr "type" "veccomplex")])
@@ -15134,7 +15162,8 @@
 (define_insn "altivec_vsumsws"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")] 135))]
+                      (match_operand:V4SI 2 "register_operand" "v")] 135))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vsumsws %0,%1,%2"
   [(set_attr "type" "veccomplex")])
@@ -15283,7 +15312,8 @@
 (define_insn "altivec_vctuxs"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
-                      (match_operand:QI 2 "immediate_operand" "i")] 153))]
+                      (match_operand:QI 2 "immediate_operand" "i")] 153))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vctuxs %0, %1, %2"
   [(set_attr "type" "vecfloat")])
@@ -15291,7 +15321,8 @@
 (define_insn "altivec_vctsxs"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
-                      (match_operand:QI 2 "immediate_operand" "i")] 154))]
+                      (match_operand:QI 2 "immediate_operand" "i")] 154))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
   "TARGET_ALTIVEC"
   "vctsxs %0, %1, %2"
   [(set_attr "type" "vecfloat")])
@@ -15514,14 +15545,16 @@
 [(set_attr "type" "veccmp")])
 
 (define_insn "altivec_mtvscr"
-  [(unspec_volatile [(match_operand:V4SI 0 "register_operand" "v")] 186)]
+  [(set (reg:SI 110)
+       (unspec_volatile:SI
+        [(match_operand:V4SI 0 "register_operand" "v")] 186))]
   "TARGET_ALTIVEC"
   "mtvscr %0"
   [(set_attr "type" "vecsimple")])
 
 (define_insn "altivec_mfvscr"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
-       (unspec_volatile:V8HI [(const_int 0)] 187))]
+       (unspec_volatile:V8HI [(reg:SI 110)] 187))]
   "TARGET_ALTIVEC"
   "mfvscr %0"
   [(set_attr "type" "vecsimple")])