Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM updates from Paolo Bonzini:
 "ARM:
   - support for chained PMU counters in guests
   - improved SError handling
   - handle Neoverse N1 erratum #1349291
   - allow side-channel mitigation status to be migrated
   - standardise most AArch64 system register accesses to msr_s/mrs_s
   - fix host MPIDR corruption on 32bit
   - selftests ckleanups

  x86:
   - PMU event {white,black}listing
   - ability for the guest to disable host-side interrupt polling
   - fixes for enlightened VMCS (Hyper-V pv nested virtualization),
   - new hypercall to yield to IPI target
   - support for passing cstate MSRs through to the guest
   - lots of cleanups and optimizations

  Generic:
   - Some txt->rST conversions for the documentation"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (128 commits)
  Documentation: virtual: Add toctree hooks
  Documentation: kvm: Convert cpuid.txt to .rst
  Documentation: virtual: Convert paravirt_ops.txt to .rst
  KVM: x86: Unconditionally enable irqs in guest context
  KVM: x86: PMU Event Filter
  kvm: x86: Fix -Wmissing-prototypes warnings
  KVM: Properly check if "page" is valid in kvm_vcpu_unmap
  KVM: arm/arm64: Initialise host's MPIDRs by reading the actual register
  KVM: LAPIC: Retry tune per-vCPU timer_advance_ns if adaptive tuning goes insane
  kvm: LAPIC: write down valid APIC registers
  KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
  KVM: doc: Add API documentation on the KVM_REG_ARM_WORKAROUNDS register
  KVM: arm/arm64: Add save/restore support for firmware workaround state
  arm64: KVM: Propagate full Spectre v2 workaround state to KVM guests
  KVM: arm/arm64: Support chained PMU counters
  KVM: arm/arm64: Remove pmc->bitmask
  KVM: arm/arm64: Re-create event when setting counter value
  KVM: arm/arm64: Extract duplicated code to own function
  KVM: arm/arm64: Rename kvm_pmu_{enable/disable}_counter functions
  KVM: LAPIC: ARBPRI is a reserved register for x2APIC
  ...

diff --cc Documentation/arm64/silicon-errata.rst
index c792774,0000000..3e57d09
mode 100644,000000..100644
--- 1/Documentation/arm64/silicon-errata.rst
--- /dev/null
+++ b/Documentation/arm64/silicon-errata.rst
@@@ -1,131 -1,0 +1,133 @@@
 +=======================================
 +Silicon Errata and Software Workarounds
 +=======================================
 +
 +Author: Will Deacon <will.deacon@arm.com>
 +
 +Date  : 27 November 2015
 +
 +It is an unfortunate fact of life that hardware is often produced with
 +so-called "errata", which can cause it to deviate from the architecture
 +under specific circumstances.  For hardware produced by ARM, these
 +errata are broadly classified into the following categories:
 +
 +  ==========  ========================================================
 +  Category A  A critical error without a viable workaround.
 +  Category B  A significant or critical error with an acceptable
 +              workaround.
 +  Category C  A minor error that is not expected to occur under normal
 +              operation.
 +  ==========  ========================================================
 +
 +For more information, consult one of the "Software Developers Errata
 +Notice" documents available on infocenter.arm.com (registration
 +required).
 +
 +As far as Linux is concerned, Category B errata may require some special
 +treatment in the operating system. For example, avoiding a particular
 +sequence of code, or configuring the processor in a particular way. A
 +less common situation may require similar actions in order to declassify
 +a Category A erratum into a Category C erratum. These are collectively
 +known as "software workarounds" and are only required in the minority of
 +cases (e.g. those cases that both require a non-secure workaround *and*
 +can be triggered by Linux).
 +
 +For software workarounds that may adversely impact systems unaffected by
 +the erratum in question, a Kconfig entry is added under "Kernel
 +Features" -> "ARM errata workarounds via the alternatives framework".
 +These are enabled by default and patched in at runtime when an affected
 +CPU is detected. For less-intrusive workarounds, a Kconfig option is not
 +available and the code is structured (preferably with a comment) in such
 +a way that the erratum will not be hit.
 +
 +This approach can make it slightly onerous to determine exactly which
 +errata are worked around in an arbitrary kernel source tree, so this
 +file acts as a registry of software workarounds in the Linux Kernel and
 +will be updated when new workarounds are committed and backported to
 +stable kernels.
 +
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Implementor    | Component       | Erratum ID      | Kconfig                     |
 ++================+=================+=================+=============================+
 +| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |
 ++----------------+-----------------+-----------------+-----------------------------+
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A53      | #845719         | ARM64_ERRATUM_845719        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A57      | #852523         | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A72      | #853709         | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |
 ++----------------+-----------------+-----------------+-----------------------------+
++| ARM            | Neoverse-N1     | #1349291        | N/A                         |
+++----------------+-----------------+-----------------+-----------------------------+
 +| ARM            | MMU-500         | #841119,826419  | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX Core   | #30115          | CAVIUM_ERRATUM_30115        |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX SMMUv2 | #27704          | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX2 SMMUv3| #74             | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Cavium         | ThunderX2 SMMUv3| #126            | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |
 ++----------------+-----------------+-----------------+-----------------------------+
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Hisilicon      | Hip08 SMMU PMCG | #162001800      | N/A                         |
 ++----------------+-----------------+-----------------+-----------------------------+
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |
 ++----------------+-----------------+-----------------+-----------------------------+
 ++----------------+-----------------+-----------------+-----------------------------+
 +| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
 ++----------------+-----------------+-----------------+-----------------------------+

diff --cc Documentation/virtual/kvm/api.txt
Simple merge

diff --cc arch/arm64/include/asm/cpufeature.h
index 3d8db50,948427f..407e2bf
--- 1/arch/arm64/include/asm/cpufeature.h
--- 2/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@@ -614,12 -614,12 +614,18 @@@ static inline bool system_uses_irq_prio
               cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
  }
  
 +static inline bool system_has_prio_mask_debugging(void)
 +{
 +      return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
 +             system_uses_irq_prio_masking();
 +}
 +
+ #define ARM64_BP_HARDEN_UNKNOWN               -1
+ #define ARM64_BP_HARDEN_WA_NEEDED     0
+ #define ARM64_BP_HARDEN_NOT_REQUIRED  1
+ 
+ int get_spectre_v2_workaround_state(void);
+ 
  #define ARM64_SSBD_UNKNOWN            -1
  #define ARM64_SSBD_FORCE_DISABLE      0
  #define ARM64_SSBD_KERNEL             1

diff --cc arch/arm64/include/asm/kvm_host.h
Simple merge

diff --cc arch/arm64/include/asm/sysreg.h
Simple merge

diff --cc arch/arm64/kernel/traps.c
Simple merge

diff --cc arch/arm64/kvm/hyp/switch.c
Simple merge

diff --cc arch/s390/include/asm/kvm_host.h
Simple merge

diff --cc arch/s390/kvm/kvm-s390.c
Simple merge

diff --cc arch/x86/kvm/lapic.c
Simple merge

diff --cc arch/x86/kvm/mmu.c
Simple merge

diff --cc arch/x86/kvm/pmu.c
Simple merge

diff --cc arch/x86/kvm/vmx/nested.c
Simple merge

diff --cc arch/x86/kvm/x86.c
Simple merge

diff --cc tools/testing/selftests/kvm/x86_64/evmcs_test.c
index 241919e,dbf8265..f95c083
--- 1/tools/testing/selftests/kvm/x86_64/evmcs_test.c
--- 2/tools/testing/selftests/kvm/x86_64/evmcs_test.c
+++ b/tools/testing/selftests/kvm/x86_64/evmcs_test.c
@@@ -144,9 -144,8 +144,9 @@@ int main(int argc, char *argv[]
  
                /* Restore state in a new VM.  */
                kvm_vm_restart(vm, O_RDWR);
-               vm_vcpu_add(vm, VCPU_ID, 0, 0);
+               vm_vcpu_add(vm, VCPU_ID);
                vcpu_set_cpuid(vm, VCPU_ID, kvm_get_supported_cpuid());
 +              vcpu_ioctl(vm, VCPU_ID, KVM_ENABLE_CAP, &enable_evmcs_cap);
                vcpu_load_state(vm, VCPU_ID, state);
                run = vcpu_state(vm, VCPU_ID);
                free(state);