;; Macros
-;; This mode macro allows 31-bit and 64-bit GPR patterns to be generated
+;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
+(define_mode_macro DSI [DI SI])
;; This mode macro allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
ordered uneq unlt ungt unle unge ltgt])
+;; This macro allows to unify all 'sCOND' patterns.
+(define_code_macro SCOND [ltu gtu leu geu])
+
+
+;; This attribute handles differences in the instruction 'type' and will result
+;; in "RRE" for DImode and "RR" for SImode.
+(define_mode_attr E [(DI "E") (SI "")])
+
+;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
+;; and "lcr" in SImode.
+(define_mode_attr g [(DI "g") (SI "")])
;; ICM mask required to load MODE value into the highest subreg
;; of a SImode register.
;;
;
-; adddicc instruction pattern(s).
+; add(di|si)cc instruction pattern(s).
;
-(define_insn "*adddi3_alc_cc"
+(define_insn "*add<mode>3_alc_cc"
[(set (reg 33)
(compare
- (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_alc_comparison" ""))
+ (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_alc_comparison" ""))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- alcgr\t%0,%2
- alcg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_alc"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_alc_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "@
- alcgr\t%0,%2
- alcg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_slb_cc"
- [(set (reg 33)
- (compare
- (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_slb_comparison" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- slbgr\t%0,%2
- slbg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_slb"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_slb_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "@
- slbgr\t%0,%2
- slbg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_expand "adddicc"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand 1 "comparison_operator" "")
- (match_operand:DI 2 "register_operand" "")
- (match_operand:DI 3 "const_int_operand" "")]
- "TARGET_64BIT"
- "if (!s390_expand_addcc (GET_CODE (operands[1]),
- s390_compare_op0, s390_compare_op1,
- operands[0], operands[2],
- operands[3])) FAIL; DONE;")
-
-;
-; addsicc instruction pattern(s).
-;
-
-(define_insn "*addsi3_alc_cc"
- [(set (reg 33)
- (compare
- (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_alc_comparison" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
- alcr\t%0,%2
- alc\t%0,%2"
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_insn "*addsi3_alc"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_alc_comparison" "")))
+(define_insn "*add<mode>3_alc"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_alc_comparison" "")))
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"@
- alcr\t%0,%2
- alc\t%0,%2"
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_insn "*subsi3_slb_cc"
+(define_insn "*sub<mode>3_slb_cc"
[(set (reg 33)
(compare
- (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_slb_comparison" ""))
+ (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_slb_comparison" ""))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
- slbr\t%0,%2
- slb\t%0,%2"
+ slb<g>r\t%0,%2
+ slb<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_insn "*subsi3_slb"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_slb_comparison" "")))
+(define_insn "*sub<mode>3_slb"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_slb_comparison" "")))
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"@
- slbr\t%0,%2
- slb\t%0,%2"
+ slb<g>r\t%0,%2
+ slb<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_expand "addsicc"
- [(match_operand:SI 0 "register_operand" "")
+(define_expand "add<mode>cc"
+ [(match_operand:GPR 0 "register_operand" "")
(match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ (match_operand:GPR 2 "register_operand" "")
+ (match_operand:GPR 3 "const_int_operand" "")]
"TARGET_CPU_ZARCH"
"if (!s390_expand_addcc (GET_CODE (operands[1]),
s390_compare_op0, s390_compare_op1,
; scond instruction pattern(s).
;
-(define_insn_and_split "*sconddi"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (match_operand:DI 1 "s390_alc_comparison" ""))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (const_int 0))
- (parallel
- [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
- (match_dup 1)))
- (clobber (reg:CC 33))])]
- "")
-
-(define_insn_and_split "*scondsi"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (match_operand:SI 1 "s390_alc_comparison" ""))
+(define_insn_and_split "*scond<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (match_operand:GPR 1 "s390_alc_comparison" ""))
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
- [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
- (match_dup 1)))
- (clobber (reg:CC 33))])]
- "")
-
-(define_insn_and_split "*sconddi_neg"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (match_operand:DI 1 "s390_slb_comparison" ""))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (const_int 0))
- (parallel
- [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
+ [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
(match_dup 1)))
- (clobber (reg:CC 33))])
- (parallel
- [(set (match_dup 0) (neg:DI (match_dup 0)))
(clobber (reg:CC 33))])]
"")
-(define_insn_and_split "*scondsi_neg"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (match_operand:SI 1 "s390_slb_comparison" ""))
+(define_insn_and_split "*scond<mode>_neg"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (match_operand:GPR 1 "s390_slb_comparison" ""))
(clobber (reg:CC 33))]
"TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
- [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
- (match_dup 1)))
+ [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
+ (match_dup 1)))
(clobber (reg:CC 33))])
(parallel
- [(set (match_dup 0) (neg:SI (match_dup 0)))
+ [(set (match_dup 0) (neg:GPR (match_dup 0)))
(clobber (reg:CC 33))])]
"")
-(define_expand "sltu"
- [(match_operand:SI 0 "register_operand" "")]
- "TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
- operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
-
-(define_expand "sgtu"
- [(match_operand:SI 0 "register_operand" "")]
- "TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
- operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
-
-(define_expand "sleu"
- [(match_operand:SI 0 "register_operand" "")]
- "TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
- operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
-(define_expand "sgeu"
- [(match_operand:SI 0 "register_operand" "")]
+(define_expand "s<code>"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (SCOND (match_dup 0)
+ (match_dup 0)))]
"TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
+ "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
;;
;
-; negdi2 instruction pattern(s).
+; neg(di|si)2 instruction pattern(s).
;
-(define_expand "negdi2"
+(define_expand "neg<mode>2"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
+ [(set (match_operand:DSI 0 "register_operand" "=d")
+ (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
(clobber (reg:CC 33))])]
""
"")
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
-(define_insn "*negdi2_cc"
+(define_insn "*neg<mode>2_cc"
[(set (reg 33)
- (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
+ (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_dup 1)))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
- "lcgr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (match_dup 1)))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "lc<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
-(define_insn "*negdi2_cconly"
+(define_insn "*neg<mode>2_cconly"
[(set (reg 33)
- (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
+ (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
- "lcgr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "lc<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
-(define_insn "*negdi2_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
+(define_insn "*neg<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
(clobber (reg:CC 33))]
- "TARGET_64BIT"
- "lcgr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ ""
+ "lc<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
(define_insn_and_split "*negdi2_31"
[(set (match_operand:DI 0 "register_operand" "=d")
operands[6] = gen_label_rtx ();")
;
-; negsi2 instruction pattern(s).
-;
-
-(define_insn "*negsi2_cc"
- [(set (reg 33)
- (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (match_dup 1)))]
- "s390_match_ccmode (insn, CCAmode)"
- "lcr\t%0,%1"
- [(set_attr "op_type" "RR")])
-
-(define_insn "*negsi2_cconly"
- [(set (reg 33)
- (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=d"))]
- "s390_match_ccmode (insn, CCAmode)"
- "lcr\t%0,%1"
- [(set_attr "op_type" "RR")])
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
- ""
- "lcr\t%0,%1"
- [(set_attr "op_type" "RR")])
-
-;
; negdf2 instruction pattern(s).
;
;;
;
-; absdi2 instruction pattern(s).
+; abs(di|si)2 instruction pattern(s).
;
(define_insn "*absdi2_sign_cc"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
-(define_insn "*absdi2_cc"
- [(set (reg 33)
- (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (abs:DI (match_dup 1)))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
- "lpgr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*absdi2_cconly"
- [(set (reg 33)
- (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
- "lpgr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "absdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (abs:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "lpgr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
-;
-; abssi2 instruction pattern(s).
-;
-
-(define_insn "*abssi2_cc"
+(define_insn "*abs<mode>2_cc"
[(set (reg 33)
- (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
+ (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d")
- (abs:SI (match_dup 1)))]
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (abs:GPR (match_dup 1)))]
"s390_match_ccmode (insn, CCAmode)"
- "lpr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "lp<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
-(define_insn "*abssi2_cconly"
+(define_insn "*abs<mode>2_cconly"
[(set (reg 33)
- (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
+ (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d"))]
+ (clobber (match_scratch:GPR 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
- "lpr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "lp<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
-(define_insn "abssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (abs:SI (match_operand:SI 1 "register_operand" "d")))
+(define_insn "abs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(clobber (reg:CC 33))]
""
- "lpr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "lp<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
;
; absdf2 instruction pattern(s).
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")])
-(define_insn "*negabsdi2_cc"
- [(set (reg 33)
- (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (abs:DI (match_dup 1))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
- "lngr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*negabsdi2_cconly"
- [(set (reg 33)
- (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
- "lngr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*negabsdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "lngr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*negabssi2_cc"
+(define_insn "*negabs<mode>2_cc"
[(set (reg 33)
- (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
+ (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (abs:SI (match_dup 1))))]
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (abs:GPR (match_dup 1))))]
"s390_match_ccmode (insn, CCAmode)"
- "lnr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "ln<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
-(define_insn "*negabssi2_cconly"
+(define_insn "*negabs<mode>2_cconly"
[(set (reg 33)
- (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
+ (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d"))]
+ (clobber (match_scratch:GPR 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
- "lnr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "ln<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
-(define_insn "*negabssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
+(define_insn "*negabs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
(clobber (reg:CC 33))]
""
- "lnr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "ln<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
;
; Floating point
;;
;
-; rotldi3 instruction pattern(s).
-;
-
-(define_insn "rotldi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (rotate:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- "TARGET_64BIT"
- "rllg\t%0,%1,%Y2"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")])
-
-;
-; rotlsi3 instruction pattern(s).
+; rotl(di|si)3 instruction pattern(s).
;
-(define_insn "rotlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (rotate:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
+(define_insn "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_CPU_ZARCH"
- "rll\t%0,%1,%Y2"
+ "rll<g>\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
OSDN Git Service
