* config/sparc/predicates.md (const_compl_high_operand): New.

	* config/sparc/sparc.c (sparc_emit_set_safe_HIGH64): Rename into
	gen_safe_HIGH64.
	(sparc_emit_set_const64_quick1): Adjust for above change.
	(sparc_emit_set_const64_quick2): Likewise.
	(sparc_emit_set_const64_longway): Likewise.
	(sparc_emit_set_const64): Likewise.
	* config/sparc/sparc.md (movhi_const64_special, movsi_const64_special,
	movdi_const64_special): Delete.
	(logical constant splitters): Use const_compl_high_operand.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@99160 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 682b0ea..eaceebc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2005-05-03  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+       * config/sparc/predicates.md (const_compl_high_operand): New.
+       * config/sparc/sparc.c (sparc_emit_set_safe_HIGH64): Rename into
+       gen_safe_HIGH64.
+       (sparc_emit_set_const64_quick1): Adjust for above change.
+       (sparc_emit_set_const64_quick2): Likewise.
+       (sparc_emit_set_const64_longway): Likewise.
+       (sparc_emit_set_const64): Likewise.
+       * config/sparc/sparc.md (movhi_const64_special, movsi_const64_special,
+       movdi_const64_special): Delete.
+       (logical constant splitters): Use const_compl_high_operand.
+
 2005-05-03  Richard Guenther  <rguenth@gcc.gnu.org>
 
        * tree-ssa-ccp.c (maybe_fold_stmt_indirect): Use STRIP_TYPE_NOPS

diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 8aba0e3..58f0bb7 100644 (file)
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -68,6 +68,12 @@
        (and (match_test "INTVAL (op) & ~(HOST_WIDE_INT)0x3ff")
             (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))"))))
 
+;; Return true if OP is a constant whose 1's complement can be loaded by the
+;; sethi instruction.
+(define_predicate "const_compl_high_operand"
+  (and (match_code "const_int")
+       (and (not (match_operand 0 "small_int_operand"))
+            (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))"))))
 
 ;; Predicates for symbolic constants.
 

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 1349cc7..94ef74d 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1145,7 +1145,7 @@ sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
 /* These avoid problems when cross compiling.  If we do not
    go through all this hair then the optimizer will see
    invalid REG_EQUAL notes or in some cases none at all.  */
-static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
+static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
@@ -1155,10 +1155,10 @@ static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
    Unfortunately this leads to many missed optimizations
    during CSE.  We mask out the non-HIGH bits, and matches
    a plain movdi, to alleviate this problem.  */
-static void
-sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
+static rtx
+gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
 {
-  emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff)));
+  return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
 }
 
 static rtx
@@ -1201,7 +1201,7 @@ sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
   else
     high_bits = low_bits;
 
-  sparc_emit_set_safe_HIGH64 (temp, high_bits);
+  emit_insn (gen_safe_HIGH64 (temp, high_bits));
   if (!is_neg)
     {
       emit_insn (gen_rtx_SET (VOIDmode, op0,
@@ -1240,7 +1240,7 @@ sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
 
   if ((high_bits & 0xfffffc00) != 0)
     {
-      sparc_emit_set_safe_HIGH64 (temp, high_bits);
+      emit_insn (gen_safe_HIGH64 (temp, high_bits));
       if ((high_bits & ~0xfffffc00) != 0)
        emit_insn (gen_rtx_SET (VOIDmode, op0,
                                gen_safe_OR64 (temp, (high_bits & 0x3ff))));
@@ -1284,7 +1284,7 @@ sparc_emit_set_const64_longway (rtx op0, rtx temp,
 
   if ((high_bits & 0xfffffc00) != 0)
     {
-      sparc_emit_set_safe_HIGH64 (temp, high_bits);
+      emit_insn (gen_safe_HIGH64 (temp, high_bits));
       if ((high_bits & ~0xfffffc00) != 0)
        emit_insn (gen_rtx_SET (VOIDmode,
                                sub_temp,
@@ -1308,7 +1308,7 @@ sparc_emit_set_const64_longway (rtx op0, rtx temp,
                              gen_rtx_ASHIFT (DImode, sub_temp,
                                              GEN_INT (32))));
 
-      sparc_emit_set_safe_HIGH64 (temp2, low_bits);
+      emit_insn (gen_safe_HIGH64 (temp2, low_bits));
       if ((low_bits & ~0xfffffc00) != 0)
        {
          emit_insn (gen_rtx_SET (VOIDmode, temp3,
@@ -1597,7 +1597,7 @@ sparc_emit_set_const64 (rtx op0, rtx op1)
       gcc_assert (SPARC_SETHI_P (focus_bits));
       gcc_assert (lowest_bit_set != 10);
 
-      sparc_emit_set_safe_HIGH64 (temp, focus_bits);
+      emit_insn (gen_safe_HIGH64 (temp, focus_bits));
 
       /* If lowest_bit_set == 10 then a sethi alone could have done it.  */
       if (lowest_bit_set < 10)

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 0846579..2078c3a 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1841,12 +1841,6 @@
   ;
 })
 
-(define_insn "*movhi_const64_special"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-       (match_operand:HI 1 "const_high_operand" "K"))]
-  "TARGET_ARCH64"
-  "sethi\t%%hi(%a1), %0")
-
 (define_insn "*movhi_insn"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
        (match_operand:HI 1 "input_operand"   "rI,K,m,rJ"))]
@@ -1943,14 +1937,6 @@
   ;
 })
 
-;; This is needed to show CSE exactly which bits are set
-;; in a 64-bit register by sethi instructions.
-(define_insn "*movsi_const64_special"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (match_operand:SI 1 "const_high_operand" "K"))]
-  "TARGET_ARCH64"
-  "sethi\t%%hi(%a1), %0")
-
 (define_insn "*movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
        (match_operand:SI 1 "input_operand"   "rI,!f,K,J,m,!m,rJ,!f,J"))]
@@ -2187,14 +2173,6 @@
   [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
    (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
 
-;; This is needed to show CSE exactly which bits are set
-;; in a 64-bit register by sethi instructions.
-(define_insn "*movdi_const64_special"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (match_operand:DI 1 "const_high_operand" "N"))]
-  "TARGET_ARCH64"
-  "sethi\t%%hi(%a1), %0")
-
 (define_insn "*movdi_insn_sp64_novis"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
         (match_operand:DI 1 "input_operand"   "rI,N,J,m,rJ,e,W,e"))]
@@ -5845,7 +5823,7 @@
   "umacd\t%1, %2, %L0"
   [(set_attr "type" "imul")])
 \f
-;;- Boolean instructions
+;; Boolean instructions
 ;; We define DImode `and' so with DImode `not' we can get
 ;; DImode `andn'.  Other combinations are possible.
 
@@ -5896,9 +5874,9 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
        (and:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "const_int_operand" "")))
+               (match_operand:SI 2 "const_compl_high_operand" "")))
    (clobber (match_operand:SI 3 "register_operand" ""))]
-  "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+  ""
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
 {
@@ -5997,9 +5975,9 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
        (ior:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "const_int_operand" "")))
+               (match_operand:SI 2 "const_compl_high_operand" "")))
    (clobber (match_operand:SI 3 "register_operand" ""))]
-  "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+  ""
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
 {
@@ -6098,9 +6076,9 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
        (xor:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "const_int_operand" "")))
+               (match_operand:SI 2 "const_compl_high_operand" "")))
    (clobber (match_operand:SI 3 "register_operand" ""))]
-   "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+   ""
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
 {
@@ -6110,9 +6088,9 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
        (not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
-                       (match_operand:SI 2 "const_int_operand" ""))))
+                       (match_operand:SI 2 "const_compl_high_operand" ""))))
    (clobber (match_operand:SI 3 "register_operand" ""))]
-  "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+  ""
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
 {