[(set_attr "type" "idiv")])
\f
;; Logical instructions
+;; The logical instructions are mostly combined by using match_operator,
+;; but the plain AND insns are somewhat different because there is no
+;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
+;; those rotate-and-mask operations. Thus, the AND insns come first.
+
(define_insn "andsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
}
}")
-(define_insn "*iorsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
- (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:SI 2 "logical_operand" "r,K,L")))]
- ""
- "@
- or %0,%1,%2
- {oril|ori} %0,%1,%b2
- {oriu|oris} %0,%1,%u2"
- [(set_attr "length" "4,4,4")])
-
-(define_insn "*iorsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWERPC64"
- "@
- or. %3,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ior:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*iorsi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (match_dup 1)
- (match_dup 2)))]
- "! TARGET_POWERPC64"
- "@
- or. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ior:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-;; Split an IOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part. This is used by combine.
-
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "non_logical_cint_operand" "")))]
- ""
- [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
- (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
-"
-{
- operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
- operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-}")
-
(define_expand "xorsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
}
}")
-(define_insn "*xorsi3_internal1"
+(define_insn "*boolsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:SI 2 "logical_operand" "r,K,L")))]
+ (match_operator:SI 3 "boolean_operator"
+ [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:SI 2 "logical_operand" "r,K,L")]))]
""
"@
- xor %0,%1,%2
- {xoril|xori} %0,%1,%b2
- {xoriu|xoris} %0,%1,%u2"
- [(set_attr "length" "4,4,4")])
+ %q3 %0,%1,%2
+ {%q3il|%q3i} %0,%1,%b2
+ {%q3iu|%q3is} %0,%1,%u2")
-(define_insn "*xorsi3_internal2"
+(define_insn "*boolsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
"! TARGET_POWERPC64"
"@
- xor. %3,%1,%2
+ %q4. %3,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(clobber (match_scratch:SI 3 ""))]
"! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (xor:SI (match_dup 1)
- (match_dup 2)))
+ [(set (match_dup 3) (match_dup 4))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*xorsi3_internal3"
+(define_insn "*boolsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (xor:SI (match_dup 1)
- (match_dup 2)))]
+ (match_dup 4))]
"! TARGET_POWERPC64"
"@
- xor. %0,%1,%2
+ %q4. %0,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (xor:SI (match_dup 1) (match_dup 2)))]
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (match_dup 4))]
"! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
+ [(set (match_dup 0) (match_dup 4))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-;; Split an XOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part. This is used by combine.
+;; Split an logical operation that we can't do in one insn into two insns,
+;; each of which does one 16-bit part. This is used by combine.
(define_split
[(set (match_operand:SI 0 "gpc_reg_operand" "")
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "non_logical_cint_operand" "")))]
+ (match_operator:SI 3 "boolean_operator"
+ [(match_operand:SI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "non_logical_cint_operand" "")]))]
""
- [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
- (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
+ [(set (match_dup 0) (match_dup 4))
+ (set (match_dup 0) (match_dup 5))]
"
{
- operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
- operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
+ rtx i;
+ i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
+ operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
+ operands[1], i);
+ i = GEN_INT (INTVAL (operands[2]) & 0xffff);
+ operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
+ operands[0], i);
}")
-(define_insn "*eqvsi3_internal1"
+(define_insn "*boolcsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- ""
- "eqv %0,%1,%2")
-
-(define_insn "*eqvsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWERPC64"
- "@
- eqv. %3,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (not:SI (xor:SI (match_dup 1)
- (match_dup 2))))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*eqvsi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
- "! TARGET_POWERPC64"
- "@
- eqv. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (not:SI (xor:SI (match_dup 1)
- (match_dup 2))))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (not:SI (xor:SI (match_dup 1)
- (match_dup 2))))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*andcsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (match_operand:SI 2 "gpc_reg_operand" "r")))]
+ (match_operator:SI 3 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "logical_operand" "r")]))]
""
- "andc %0,%2,%1")
+ "%q3 %0,%2,%1")
-(define_insn "*andcsi3_internal2"
+(define_insn "*boolcsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
"! TARGET_POWERPC64"
"@
- andc. %3,%2,%1
+ %q4. %3,%2,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r")])
+ (const_int 0)))
(clobber (match_scratch:SI 3 ""))]
"! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (and:SI (not:SI (match_dup 1))
- (match_dup 2)))
+ [(set (match_dup 3) (match_dup 4))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*andcsi3_internal3"
+(define_insn "*boolcsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (not:SI (match_dup 1))
- (match_dup 2)))]
- "! TARGET_POWERPC64"
- "@
- andc. %0,%2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (not:SI (match_dup 1))
- (match_dup 2)))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (and:SI (not:SI (match_dup 1))
- (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*iorcsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (match_operand:SI 2 "gpc_reg_operand" "r")))]
- ""
- "orc %0,%2,%1")
-
-(define_insn "*iorcsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
+ (match_dup 4))]
"! TARGET_POWERPC64"
"@
- orc. %3,%2,%1
+ %q4. %0,%2,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ior:SI (not:SI (match_dup 1))
- (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*iorcsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
- "! TARGET_POWERPC64"
- "@
- orc. %0,%2,%1
- #"
- [(set_attr "type" "compare")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (not:SI (match_dup 1))
- (match_dup 2)))]
+ (match_dup 4))]
"! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ior:SI (not:SI (match_dup 1))
- (match_dup 2)))
+ [(set (match_dup 0) (match_dup 4))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*nandsi3_internal1"
+(define_insn "*boolccsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+ (match_operator:SI 3 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "logical_operand" "r"))]))]
""
- "nand %0,%1,%2")
+ "%q3 %0,%1,%2")
-(define_insn "*nandsi3_internal2"
+(define_insn "*boolccsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+ (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
"! TARGET_POWERPC64"
"@
- nand. %3,%1,%2
+ %q4. %3,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))])
+ (const_int 0)))
(clobber (match_scratch:SI 3 ""))]
"! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ior:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))
+ [(set (match_dup 3) (match_dup 4))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*nandsi3_internal3"
+(define_insn "*boolccsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+ (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))]
- "! TARGET_POWERPC64"
- "@
- nand. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ior:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*norsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- ""
- "nor %0,%1,%2")
-
-(define_insn "*norsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
+ (match_dup 4))]
"! TARGET_POWERPC64"
"@
- nor. %3,%1,%2
+ %q4. %0,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (and:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*norsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
+ (compare:CC (match_operator:SI 4 "boolean_operator"
+ [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+ (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))]
- "! TARGET_POWERPC64"
- "@
- nor. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))]
+ (match_dup 4))]
"! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (and:SI (not:SI (match_dup 1))
- (not:SI (match_dup 2))))
+ [(set (match_dup 0) (match_dup 4))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
(define_expand "iordi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_u_cint_operand" "")))]
+ (match_operand:DI 2 "reg_or_cint_operand" "")))]
"TARGET_POWERPC64"
"
{
- if (GET_CODE (operands[2]) == CONST_INT
- && ! logical_u_operand (operands[2], DImode))
+ if (non_logical_cint_operand (operands[2], DImode))
{
- HOST_WIDE_INT value = INTVAL (operands[2]);
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (DImode));
-
- emit_insn (gen_iordi3 (tmp, operands[1],
- GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
- emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
- DONE;
- }
- else if (GET_CODE (operands[2]) == CONST_DOUBLE
- && ! logical_u_operand (operands[2], DImode))
- {
- HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
+ HOST_WIDE_INT value;
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (DImode));
- emit_insn (gen_iordi3 (tmp, operands[1],
- immed_double_const (value
- & (~ (HOST_WIDE_INT) 0xffff),
- 0, DImode)));
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ value = INTVAL (operands[2]);
+ emit_insn (gen_iordi3 (tmp, operands[1],
+ GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
+ }
+ else if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ {
+ value = CONST_DOUBLE_LOW (operands[2]);
+ emit_insn (gen_iordi3 (tmp, operands[1],
+ immed_double_const (value
+ & (~ (HOST_WIDE_INT) 0xffff),
+ 0, DImode)));
+ }
emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
DONE;
}
}")
-(define_insn "*iordi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
- (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:DI 2 "logical_u_operand" "r,K,JF")))]
- "TARGET_POWERPC64"
- "@
- or %0,%1,%2
- ori %0,%1,%b2
- oris %0,%1,%u2")
-
-(define_insn "*iordi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_POWERPC64"
- "@
- or. %3,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ior:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*iordi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ior:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64"
- "@
- or. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (ior:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ior:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-;; Split an IOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part. This is used by combine.
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "non_logical_u_cint_operand" "")))]
- "TARGET_POWERPC64"
- [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
- (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
-"
-{
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
- {
- HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
- operands[3] = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
- 0, DImode);
- operands[4] = GEN_INT (value & 0xffff);
- }
- else
- {
- operands[3] = GEN_INT (INTVAL (operands[2])
- & (~ (HOST_WIDE_INT) 0xffff));
- operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
- }
-}")
-
(define_expand "xordi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_u_cint_operand" "")))]
+ (match_operand:DI 2 "reg_or_cint_operand" "")))]
"TARGET_POWERPC64"
"
{
- if (GET_CODE (operands[2]) == CONST_INT
- && ! logical_u_operand (operands[2], DImode))
+ if (non_logical_cint_operand (operands[2], DImode))
{
- HOST_WIDE_INT value = INTVAL (operands[2]);
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (DImode));
-
- emit_insn (gen_xordi3 (tmp, operands[1],
- GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
- emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
- DONE;
- }
- else if (GET_CODE (operands[2]) == CONST_DOUBLE
- && ! logical_u_operand (operands[2], DImode))
- {
- HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
+ HOST_WIDE_INT value;
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (DImode));
- emit_insn (gen_xordi3 (tmp, operands[1],
- immed_double_const (value
- & (~ (HOST_WIDE_INT) 0xffff),
- 0, DImode)));
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ value = INTVAL (operands[2]);
+ emit_insn (gen_xordi3 (tmp, operands[1],
+ GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
+ }
+ else if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ {
+ value = CONST_DOUBLE_LOW (operands[2]);
+ emit_insn (gen_xordi3 (tmp, operands[1],
+ immed_double_const (value
+ & (~ (HOST_WIDE_INT) 0xffff),
+ 0, DImode)));
+ }
emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
DONE;
}
}")
-(define_insn "*xordi3_internal1"
+(define_insn "*booldi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
- (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:DI 2 "logical_u_operand" "r,K,JF")))]
+ (match_operator:DI 3 "boolean_operator"
+ [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
"TARGET_POWERPC64"
"@
- xor %0,%1,%2
- xori %0,%1,%b2
- xoris %0,%1,%u2")
+ %q3 %0,%1,%2
+ %q3i %0,%1,%b2
+ %q3is %0,%1,%u2")
-(define_insn "*xordi3_internal2"
+(define_insn "*booldi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"@
- xor. %3,%1,%2
+ %q4. %3,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (xor:DI (match_dup 1) (match_dup 2)))
+ [(set (match_dup 3) (match_dup 4))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*xordi3_internal3"
+(define_insn "*booldi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (xor:DI (match_dup 1) (match_dup 2)))]
+ (match_dup 4))]
"TARGET_POWERPC64"
"@
- xor. %0,%1,%2
+ %q4. %0,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (xor:DI (match_dup 1) (match_dup 2)))]
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (match_dup 4))]
"TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (xor:DI (match_dup 1) (match_dup 2)))
+ [(set (match_dup 0) (match_dup 4))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-;; Split an XOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part. This is used by combine.
+;; Split an logical operation that we can't do in one insn into two insns,
+;; each of which does one 16-bit part. This is used by combine.
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
- (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "non_logical_u_cint_operand" "")))]
+ (match_operator:DI 3 "boolean_operator"
+ [(match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "non_logical_cint_operand" "")]))]
"TARGET_POWERPC64"
- [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
- (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
+ [(set (match_dup 0) (match_dup 4))
+ (set (match_dup 0) (match_dup 5))]
"
{
+ rtx i3,i4;
+
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
- operands[3] = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
+ i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
0, DImode);
- operands[4] = GEN_INT (value & 0xffff);
+ i4 = GEN_INT (value & 0xffff);
}
else
{
- operands[3] = GEN_INT (INTVAL (operands[2])
+ i3 = GEN_INT (INTVAL (operands[2])
& (~ (HOST_WIDE_INT) 0xffff));
- operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
+ i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
}
+ operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
+ operands[1], i3);
+ operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
+ operands[0], i4);
}")
-(define_insn "*eqvdi3_internal1"
+(define_insn "*boolcdi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
- (match_operand:DI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC64"
- "eqv %0,%1,%2")
-
-(define_insn "*eqvdi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_POWERPC64"
- "@
- eqv. %3,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (not:DI (xor:DI (match_dup 1) (match_dup 2))))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*eqvdi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
- "TARGET_POWERPC64"
- "@
- eqv. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (not:DI (xor:DI (match_dup 1) (match_dup 2))))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*andcdi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ (match_operator:DI 3 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "logical_operand" "r")]))]
"TARGET_POWERPC64"
- "andc %0,%2,%1")
+ "%q3 %0,%1,%2")
-(define_insn "*andcdi3_internal2"
+(define_insn "*boolcdi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"@
- andc. %3,%2,%1
+ %q4. %3,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r")])
+ (const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (and:DI (not:DI (match_dup 1)) (match_dup 2)))
+ [(set (match_dup 3) (match_dup 4))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*andcdi3_internal3"
+(define_insn "*boolcdi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
+ (match_dup 4))]
"TARGET_POWERPC64"
"@
- andc. %0,%2,%1
+ %q4. %0,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (and:DI (not:DI (match_dup 1)) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*iorcdi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC64"
- "orc %0,%2,%1")
-
-(define_insn "*iorcdi3_inernal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_POWERPC64"
- "@
- orc. %3,%2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ior:DI (not:DI (match_dup 1)) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*iorcdi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
- "TARGET_POWERPC64"
- "@
- orc. %0,%2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
+ (match_dup 4))]
"TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ior:DI (not:DI (match_dup 1)) (match_dup 2)))
+ [(set (match_dup 0) (match_dup 4))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*nanddi3_internal1"
+(define_insn "*boolccdi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
+ (match_operator:DI 3 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (not:DI (match_operand:DI 2 "logical_operand" "r"))]))]
"TARGET_POWERPC64"
- "nand %0,%1,%2")
+ "%q3 %0,%1,%2")
-(define_insn "*nanddi3_internal2"
+(define_insn "*boolccdi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
+ (const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"@
- nand. %3,%1,%2
+ %q4. %3,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))])
+ (const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))
+ [(set (match_dup 3) (match_dup 4))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*nanddi3_internal3"
+(define_insn "*boolccdi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
- "TARGET_POWERPC64"
- "@
- nand. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*nordi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC64"
- "nor %0,%1,%2")
-
-(define_insn "*nordi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
+ (match_dup 4))]
"TARGET_POWERPC64"
"@
- nor. %3,%1,%2
+ %q4. %0,%1,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*nordi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
- (const_int 0)))
+ (compare:CC (match_operator:DI 4 "boolean_operator"
+ [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
- "TARGET_POWERPC64"
- "@
- nor. %0,%1,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-\f
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
+ (match_dup 4))]
"TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))
+ [(set (match_dup 0) (match_dup 4))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-
+\f
;; Now define ways of moving data around.
;; Elf specific ways of loading addresses for non-PIC code.