* config/m68hc11/m68hc11.md ("mulqi3"): Allow address register to

	avoid reload problems; define split for it.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@63680 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 03eb0fa..f63a647 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2003-03-02  Stephane Carrez  <stcarrez@nerim.fr>
 
+       * config/m68hc11/m68hc11.md ("mulqi3"): Allow address register to
+       avoid reload problems; define split for it.
+
+2003-03-02  Stephane Carrez  <stcarrez@nerim.fr>
+
        * config/m68hc11/m68hc11.c (m68hc11_shift_operator): New function.
        * config/m68hc11/m68hc11-protos.h (m68hc11_shift_operator): Declare.
        * config/m68hc11/m68hc11.h (PREDICATE_CODES): Register.

diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index 8117d48..4841aeb 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -2894,12 +2894,15 @@
 }")
 
 (define_insn "mulqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-        (mult:QI (match_operand:QI 1 "nonimmediate_operand" "dum")
-                (match_operand:QI 2 "nonimmediate_operand" "dum")))]
+  [(set (match_operand:QI 0 "register_operand" "=d,*x,*y")
+        (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%dum,0,0")
+                (match_operand:QI 2 "general_operand" "dium,*xium,*yium")))]
   ""
   "*
 {
+  if (A_REG_P (operands[0]))
+    return \"#\";
+
   if (D_REG_P (operands[1]) && D_REG_P (operands[2]))
     {
       output_asm_insn (\"tba\", operands);
@@ -2925,6 +2928,28 @@
   return \"mul\";
 }")
 
+(define_split
+  [(set (match_operand:QI 0 "hard_addr_reg_operand" "")
+        (mult:QI (match_operand:QI 1 "general_operand" "")
+                (match_operand:QI 2 "general_operand" "")))]
+  "z_replacement_completed == 2"
+  [(parallel [(set (reg:HI D_REGNUM) (match_dup 3))
+             (set (match_dup 3) (reg:HI D_REGNUM))])
+   (set (reg:QI D_REGNUM) (mult:QI (match_dup 5) (match_dup 6)))
+   (parallel [(set (reg:HI D_REGNUM) (match_dup 3))
+              (set (match_dup 3) (reg:HI D_REGNUM))])]
+  "
+   operands[3] = gen_rtx (REG, HImode, REGNO (operands[0]));
+   if (A_REG_P (operands[1]))
+     operands[5] = gen_rtx (REG, QImode, HARD_D_REGNUM);
+   else
+     operands[5] = operands[1];
+   if (A_REG_P (operands[2]))
+     operands[6] = gen_rtx (REG, QImode, HARD_D_REGNUM);
+   else
+     operands[6] = operands[2];
+  ")
+
 (define_insn "mulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=d,d")
         (mult:HI (sign_extend:HI