(do_pld): Update comment.
(insns): Add support for pldw.
(arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support
MP extension.
(arm_extensions): Add 'mp' extension.
(aeabi_set_public_attributes): Emit correct build attribute when
MP extension is enabled.
* gas/doc/c-arm.texi: Update for MP extensions.
* gas/testsuite/gas/arm/arch7a-mp.d: Add.
* gas/testsuite/gas/arm/arch7ar-mp.s: Likewise.
* gas/testsuite/gas/arm/arch7r-mp.d: Likewise.
* gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise.
* gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add.
* gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise.
* include/opcode/arm.h (ARM_EXT_MP): Add.
(ARM_ARCH_V7A_MP): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add support for pldw.
(thumb32_opcodes): Likewise.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * config/tc-arm.c (arm_ext_mp): Add.
+ (do_pld): Update comment.
+ (insns): Add support for pldw.
+ (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support
+ MP extension.
+ (arm_extensions): Add 'mp' extension.
+ (aeabi_set_public_attributes): Emit correct build attribute when
+ MP extension is enabled.
+ * doc/c-arm.texi: Update for MP extensions.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* config/tc-arm.c (md_pseduo_table): Add .arch_extension directive.
(arm_option_extension_value_table): Add.
(arm_extensions): Change type.
static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
static const arm_feature_set arm_ext_m =
ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0);
+static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
static const arm_feature_set arm_arch_any = ARM_ANY;
static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
}
/* ARMv5TE: Preload-Cache
+ MP Extensions: Preload for write
- PLD <addr_mode>
Syntactically, like LDR with B=1, W=0, L=1. */
TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_mp
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_mp
+
+ TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
{"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
{"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
{"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
- {"cortex-a5", ARM_ARCH_V7A, FPU_NONE, "Cortex-A5"},
+ {"cortex-a5", ARM_ARCH_V7A_MP, FPU_NONE, "Cortex-A5"},
{"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3
| FPU_NEON_EXT_V1),
"Cortex-A8"},
- {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3
+ {"cortex-a9", ARM_ARCH_V7A_MP, ARM_FEATURE (0, FPU_VFP_V3
| FPU_NEON_EXT_V1),
"Cortex-A9"},
- {"cortex-a15", ARM_ARCH_V7A, FPU_ARCH_NEON_VFP_V4,
+ {"cortex-a15", ARM_ARCH_V7A_MP, FPU_ARCH_NEON_VFP_V4,
"Cortex-A15"},
{"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
{"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
{"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
{"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
+ {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
+ ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
{"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
- {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
+ {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
};
/* ISA floating-point and Advanced SIMD extensions. */
aeabi_set_attribute_int (Tag_DIV_use, 2); */
else
aeabi_set_attribute_int (Tag_DIV_use, 1);
+
+ /* Tag_MP_extension_use. */
+ if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
+ aeabi_set_attribute_int (Tag_MPextension_use, 1);
}
/* Add the default contents for the .ARM.attributes section. */
Multiple extensions may be specified, separated by a @code{+}. The
extensions should be specified in ascending alphabetical order.
+Some extensions may be restricted to particular architectures; this is
+documented in the list of extensions below.
+
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending @code{no} to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
@code{iwmmxt},
@code{iwmmxt2},
@code{maverick},
+@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
and
@code{xscale}.
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * gas/arm/arch7a-mp.d: Add.
+ * gas/arm/arch7ar-mp.s: Likewise.
+ * gas/arm/arch7r-mp.d: Likewise.
+ * gas/arm/armv2-mp-bad.d: Likewise.
+ * gas/arm/armv2-mp-bad.l: Likewise.
+ * gas/arm/attr-march-all.d: Update for MP extension.
+ * gas/arm/attr-march-armv7-a+mp.d: Add.
+ * gas/arm/attr-march-armv7-r+mp.d: Likewise.
+
2010-09-23 Alan Modra <amodra@gmail.com>
* gas/all/gas.exp: Update "forward" and "redef3" xfails.
--- /dev/null
+#name: ARM V7-A+MP instructions
+#as: -march=armv7-a+mp
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: arch7ar-mp.s
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
+0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
+0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
+0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
+0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
+0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
+0[0-9a-f]+ <[^>]+> f790f001 pldw \[r0, r1\]
+0[0-9a-f]+ <[^>]+> f790f00e pldw \[r0, lr\]
+0[0-9a-f]+ <[^>]+> f790f100 pldw \[r0, r0, lsl #2\]
+0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
+0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
+0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
+0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
+0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
+0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
+0[0-9a-f]+ <[^>]+> f83e f000 pldw \[lr, r0\]
+0[0-9a-f]+ <[^>]+> f830 f001 pldw \[r0, r1\]
+0[0-9a-f]+ <[^>]+> f830 f00e pldw \[r0, lr\]
+0[0-9a-f]+ <[^>]+> f830 f030 pldw \[r0, r0, lsl #3\]
--- /dev/null
+ @ Test MP Extension instructions
+ .text
+
+label1:
+ pldw [r0, #0]
+ pldw [r14, #0]
+ pldw [r1, #0]
+ pldw [r0, #4095]
+ pldw [r0, #-4095]
+
+ pldw [r0, r0]
+ pldw [r1, r0]
+ pldw [r14, r0]
+ pldw [r0, r1]
+ pldw [r0, r14]
+ pldw [r0, r0, lsl #2]
+
+ .thumb
+ .thumb_func
+label2:
+ pldw [r0, #0]
+ pldw [r14, #0]
+ pldw [r1, #0]
+ pldw [r0, #4095]
+ pldw [r0, #-255]
+
+ pldw [r0, r0]
+ pldw [r1, r0]
+ pldw [r14, r0]
+ pldw [r0, r1]
+ pldw [r0, r14]
+ pldw [r0, r0, lsl #3]
+
--- /dev/null
+#name: ARM V7-R+MP instructions
+#as: -march=armv7-r+mp
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: arch7ar-mp.s
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
+0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
+0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
+0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
+0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
+0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
+0[0-9a-f]+ <[^>]+> f790f001 pldw \[r0, r1\]
+0[0-9a-f]+ <[^>]+> f790f00e pldw \[r0, lr\]
+0[0-9a-f]+ <[^>]+> f790f100 pldw \[r0, r0, lsl #2\]
+0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
+0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
+0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
+0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
+0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
+0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
+0[0-9a-f]+ <[^>]+> f83e f000 pldw \[lr, r0\]
+0[0-9a-f]+ <[^>]+> f830 f001 pldw \[r0, r1\]
+0[0-9a-f]+ <[^>]+> f830 f00e pldw \[r0, lr\]
+0[0-9a-f]+ <[^>]+> f830 f030 pldw \[r0, r0, lsl #3\]
--- /dev/null
+#name: ARM MP Extension errors
+#source: blank.s
+#as: -march=armv2+mp
+#error-output: armv2-mp-bad.l
--- /dev/null
+Assembler messages:
+[^:]*: extension does not apply to the base architecture
+[^:]*: unrecognized option -march=armv2\+mp
Tag_CPU_arch_profile: Application
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
--- /dev/null
+# name: attributes for -march=armv7-a+mp
+# source: blank.s
+# as: -march=armv7-a+mp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "7-A"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Not allowed
--- /dev/null
+# name: attributes for -march=armv7-r+mp
+# source: blank.s
+# as: -march=armv7-r+mp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "7-R"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm.h (ARM_EXT_MP): Add.
+ (ARM_ARCH_V7A_MP): Likewise.
+
2010-09-22 Mike Frysinger <vapier@gentoo.org>
* bfin.h: Declare pseudoChr structs/defines.
#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
not in v7-M. */
+#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
+#define ARM_ARCH_V7A_MP ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP, 0)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add support for pldw.
+ (thumb32_opcodes): Likewise.
+
2010-09-22 Robin Getz <robin.getz@analog.com>
* bfin-dis.c (fmtconst): Cast address to 32bits.
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
+ /* MP Extension instructions. */
+ {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
+
/* V7 instructions. */
{ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
{ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
{ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
+ /* MP Extension instructions. */
+ {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
+
/* Instructions defined in the basic V6T2 set. */
{ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
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