PR target/46051

	* config/i386/sse.md (vec_interleave_highv4df): Fix third RTX of
	generated sequence to match *avx_vperm2f128<mode>_nozero.
	(vec_interleave_lowv4df): Ditto.
	(vec_interleave_highv8sf): Ditto.
	(vec_interleave_lowv8sf): Ditto.

testsuite/ChangeLog:

	PR target/46051
	* gcc.target/i386/pr46051.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@165599 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dd7a108..0eb36e6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2010-10-17  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/46051
+       * config/i386/sse.md (vec_interleave_highv4df): Fix third RTX of
+       generated sequence to match *avx_vperm2f128<mode>_nozero.
+       (vec_interleave_lowv4df): Ditto.
+       (vec_interleave_highv8sf): Ditto.
+       (vec_interleave_lowv8sf): Ditto.
+
 2010-10-17  Kai Tietz  <kai.tietz@onevision.com>
 
        * libgcov.c (create_file_directory): Enable it for win32 case.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index db5e4de..2be9903 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3574,15 +3574,14 @@
                     (const_int 6) (const_int 14)
                     (const_int 7) (const_int 15)])))
    (set (match_operand:V8SF 0 "register_operand" "")
-       (vec_concat:V8SF
-         (vec_select:V4SF
+       (vec_select:V8SF
+         (vec_concat:V16SF
            (match_dup 3)
-           (parallel [(const_int 4) (const_int 5)
-                      (const_int 6) (const_int 7)]))
-         (vec_select:V4SF
-           (match_dup 4)
-           (parallel [(const_int 4) (const_int 5)
-                      (const_int 6) (const_int 7)]))))]
+           (match_dup 4))
+         (parallel [(const_int 4) (const_int 5)
+                    (const_int 6) (const_int 7)
+                    (const_int 12) (const_int 13)
+                    (const_int 14) (const_int 15)])))]
  "TARGET_AVX"
 {
   operands[3] = gen_reg_rtx (V8SFmode);
@@ -3653,15 +3652,14 @@
                     (const_int 6) (const_int 14)
                     (const_int 7) (const_int 15)])))
    (set (match_operand:V8SF 0 "register_operand" "")
-       (vec_concat:V8SF
-         (vec_select:V4SF
+       (vec_select:V8SF
+         (vec_concat:V16SF
            (match_dup 3)
-           (parallel [(const_int 0) (const_int 1)
-                      (const_int 2) (const_int 3)]))
-         (vec_select:V4SF
-           (match_dup 4)
-           (parallel [(const_int 0) (const_int 1)
-                      (const_int 2) (const_int 3)]))))]
+           (match_dup 4))
+         (parallel [(const_int 0) (const_int 1)
+                    (const_int 2) (const_int 3)
+                    (const_int 8) (const_int 9)
+                    (const_int 10) (const_int 11)])))]
  "TARGET_AVX"
 {
   operands[3] = gen_reg_rtx (V8SFmode);
@@ -4583,13 +4581,12 @@
          (parallel [(const_int 1) (const_int 5)
                     (const_int 3) (const_int 7)])))
    (set (match_operand:V4DF 0 "register_operand" "")
-       (vec_concat:V4DF
-         (vec_select:V2DF
+       (vec_select:V4DF
+         (vec_concat:V8DF
            (match_dup 3)
-           (parallel [(const_int 2) (const_int 3)]))
-         (vec_select:V2DF
-           (match_dup 4)
-           (parallel [(const_int 2) (const_int 3)]))))]
+           (match_dup 4))
+         (parallel [(const_int 2) (const_int 3)
+                    (const_int 6) (const_int 7)])))]
  "TARGET_AVX"
 {
   operands[3] = gen_reg_rtx (V4DFmode);
@@ -4718,13 +4715,12 @@
          (parallel [(const_int 1) (const_int 5)
                     (const_int 3) (const_int 7)])))
    (set (match_operand:V4DF 0 "register_operand" "")
-       (vec_concat:V4DF
-         (vec_select:V2DF
+       (vec_select:V4DF
+         (vec_concat:V8DF
            (match_dup 3)
-           (parallel [(const_int 0) (const_int 1)]))
-         (vec_select:V2DF
-           (match_dup 4)
-           (parallel [(const_int 0) (const_int 1)]))))]
+           (match_dup 4))
+         (parallel [(const_int 0) (const_int 1)
+                    (const_int 4) (const_int 5)])))]
  "TARGET_AVX"
 {
   operands[3] = gen_reg_rtx (V4DFmode);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7004ca2..eb4bbb9 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-10-17  Uros Bizjak  <ubizjak@gmail.com>
+           H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/46051
+       * gcc.target/i386/pr46051.c: New test.
+
 2010-10-17  Nicola Pero  <nicola.pero@meta-innovation.com>
 
        * obj-c++.dg/gnu-api-2-class.mm: New.

diff --git a/gcc/testsuite/gcc.target/i386/pr46051.c b/gcc/testsuite/gcc.target/i386/pr46051.c
new file mode 100644 (file)
index 0000000..2da432f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr46051.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+
+double val1[4][2], val2[4][2], chk[4][2];
+
+void
+foo (void)
+{
+  int i, j;
+  for (i = 0; i < 4; i++)
+    {
+      double tmp = 0;
+      for (j = 0; j < 2; j++)
+       tmp += val1[i][j] * val2[i][j];
+      for (j = 0; j < 2; j++)
+       chk[i][j] = tmp;
+    }
+}
+
+float val1f[8][2], val2f[8][2], chkf[8][2];
+
+void
+foof (void)
+{
+  int i, j;
+  for (i = 0; i < 8; i++)
+    {
+      float tmp = 0;
+      for (j = 0; j < 2; j++)
+       tmp += val1f[i][j] * val2f[i][j];
+      for (j = 0; j < 2; j++)
+       chkf[i][j] = tmp;
+    }
+}