+2007-07-03 Richard Sandiford <richard@codesourcery.com>
+ David Ung <davidu@mips.com>
+
+ * doc/invoke.texi: Replace -march=24kf with -march=24kf2_1 and
+ -march=24kx with -march=24kf1_1. Likewise 24ke[fx], 34k[fx]
+ and 74k[fx]. Document aliases for the new options.
+ * config/mips/mips.h (PROCESSOR_24KF): Rename to...
+ (PROCESSOR_24KF2_1): ...this.
+ (PROCESSOR_24KX): Rename to...
+ (PROCESSOR_24KF1_1): ...this.
+ (PROCESSOR_74KF): Rename to...
+ (PROCESSOR_74KF2_1): ...this.
+ (PROCESSOR_74KX): Rename to...
+ (PROCESSOR_74KF1_1): ...this.
+ (TUNE_74K): Update PROCESSOR_* names.
+ * config/mips/mips.c (mips_cpu_info): Add 24kf2_1 as a synonym
+ for 24kf. Add 24kf1_1 and 24kfx as synonyms for 24kx. Likewise
+ the 24ke*, 34k* and 74k* processors. Update PROCESSOR_* names.
+ (mips_rtx_cost_data): Update processor names in comments.
+ (mips_issue_rate): Update PROCESSOR_* names.
+ * config/mips/mips.md (cpu): Rename 24kf to 24kf2_1, 24kx to
+ 24kf1_1, 74kf to 74kf2_1 and 74kx to 74kf1_1.
+ * config/mips/24k.md: Rename FPU-related r24k_* insn reservations
+ to r24kf2_1_*. Rename r24kx_* insn reservations to r24kf1_1_*.
+ Update cpu attribute names.
+ (r24k_fpu_iss): Rename this reservation to...
+ (r24kf2_1_fpu_iss): ...this and update all uses.
+ (r24kx_fpu_iss): Rename this reservation to...
+ (r24kf1_1_fpu_iss): ...this and update all uses.
+ * config/mips/74k.md: Rename FPU-related r74kf_* insn reservations
+ to r74kf2_1_*. Rename r74kx_* insn reservations to r74kf1_1_*.
+ Update cpu attribute names.
+
2007-07-01 Kaz Kojima <kkojima@gcc.gnu.org>
* config/m32r/constraints.md: New file.
;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
;; and David Ung (davidu@mips.com)
;;
-;; The 24K is a single-issue processor with a half-clocked fpu.
-;; The 24Kx is 24k with 1:1 clocked fpu.
+;; The 24kf2_1 is a single-issue processor with a half-clocked fpu.
+;; The 24kf1_1 is 24k with 1:1 clocked fpu.
;;
;; References:
;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
(define_insn_reservation "r24k_int_load" 2
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "load"))
"r24k_iss+r24k_ixu_arith")
;; (movn/movz is not matched, we'll need to split condmov to
;; differentiate between integer/float moves)
(define_insn_reservation "r24k_int_arith" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "arith,const,nop,shift,slt"))
"r24k_iss+r24k_ixu_arith")
;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
;; 3a. jr/jalr consumer
(define_insn_reservation "r24k_int_jump" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "call,jump"))
"r24k_iss+r24k_ixu_arith")
;; 3b. branch consumer
(define_insn_reservation "r24k_int_branch" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "branch"))
"r24k_iss+r24k_ixu_arith")
;; 4. MDU: fully pipelined multiplier
;; mult - delivers result to hi/lo in 1 cycle (pipelined)
(define_insn_reservation "r24k_int_mult" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "imul"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
(define_insn_reservation "r24k_int_madd" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "imadd"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mul - delivers result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mul3" 5
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "imul3"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mfhilo" 5
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "mfhilo"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
(define_insn_reservation "r24k_int_mthilo" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "mthilo"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
;; 8bit, but is tricky to identify.
(define_insn_reservation "r24k_int_div" 36
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "idiv"))
"r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
;; 5. Cop: cfc1, di, ei, mfc0, mtc0
;; (Disabled until we add proper cop0 support)
;;(define_insn_reservation "r24k_int_cop" 3
-;; (and (eq_attr "cpu" "24k,24kx")
+;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
;; (eq_attr "type" "cop0"))
;; "r24k_iss+r24k_ixu_arith")
;; 6. Store
(define_insn_reservation "r24k_int_store" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(and (eq_attr "type" "store")
(eq_attr "mode" "!unknown")))
"r24k_iss+r24k_ixu_arith")
;; against store_data_bypass_p, which would then fail because cprestore
;; does not have a normal SET pattern.
(define_insn_reservation "r24k_unknown_store" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(and (eq_attr "type" "store")
(eq_attr "mode" "unknown")))
"r24k_iss+r24k_ixu_arith")
;; 7. Multiple instructions
(define_insn_reservation "r24k_int_multi" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "multi"))
"r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
;; rtls. They do not really affect scheduling latency, (blockage affects
;; scheduling via log links, but not used here).
(define_insn_reservation "r24k_int_unknown" 0
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "unknown"))
"r24k_iss")
;; 9. Prefetch
(define_insn_reservation "r24k_int_prefetch" 1
- (and (eq_attr "cpu" "24kc,24kf,24kx")
+ (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
(eq_attr "type" "prefetch,prefetchx"))
"r24k_iss+r24k_ixu_arith")
;; These timings are therefore twice the values in the 24K manual,
;; which are quoted in fpu clocks.
;;
-;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
+;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
;; the unscaled timings
-(define_reservation "r24k_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
+(define_reservation "r24kf2_1_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
;; fadd, fabs, fneg
-(define_insn_reservation "r24k_fadd" 8
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fadd" 8
+ (and (eq_attr "cpu" "24kf2_1")
(eq_attr "type" "fadd,fabs,fneg"))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fmove, fcmove
-(define_insn_reservation "r24k_fmove" 8
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fmove" 8
+ (and (eq_attr "cpu" "24kf2_1")
(eq_attr "type" "fmove,condmove"))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fload
-(define_insn_reservation "r24k_fload" 6
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fload" 6
+ (and (eq_attr "cpu" "24kf2_1")
(eq_attr "type" "fpload,fpidxload"))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fstore
-(define_insn_reservation "r24k_fstore" 2
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fstore" 2
+ (and (eq_attr "cpu" "24kf2_1")
(eq_attr "type" "fpstore"))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fmul, fmadd
-(define_insn_reservation "r24k_fmul_sf" 8
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fmul_sf" 8
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
-(define_insn_reservation "r24k_fmul_df" 10
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fmul_df" 10
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
- "r24k_fpu_iss,(r24k_fpu_arith*2)")
+ "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)")
;; fdiv, fsqrt, frsqrt
-(define_insn_reservation "r24k_fdiv_sf" 34
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fdiv_sf" 34
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
- "r24k_fpu_iss,(r24k_fpu_arith*26)")
+ "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)")
-(define_insn_reservation "r24k_fdiv_df" 64
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fdiv_df" 64
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
- "r24k_fpu_iss,(r24k_fpu_arith*56)")
+ "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)")
;; frsqrt
-(define_insn_reservation "r24k_frsqrt_df" 70
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_frsqrt_df" 70
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
- "r24k_fpu_iss,(r24k_fpu_arith*60)")
+ "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)")
;; fcmp
-(define_insn_reservation "r24k_fcmp" 4
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcmp" 4
+ (and (eq_attr "cpu" "24kf2_1")
(eq_attr "type" "fcmp"))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
-(define_bypass 2 "r24k_fcmp" "r24k_fmove")
+(define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove")
;; fcvt (cvt.d.s, cvt.[sd].[wl])
-(define_insn_reservation "r24k_fcvt_i2f_s2d" 8
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fcvt (cvt.s.d)
-(define_insn_reservation "r24k_fcvt_s2d" 12
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcvt_s2d" 12
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "D2S")))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fcvt (cvt.[wl].[sd], etc)
-(define_insn_reservation "r24k_fcvt_f2i" 10
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcvt_f2i" 10
+ (and (eq_attr "cpu" "24kf2_1")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "S2I,D2I")))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
-(define_insn_reservation "r24k_fxfer" 4
- (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fxfer" 4
+ (and (eq_attr "cpu" "24kf2_1")
(eq_attr "type" "mfc,mtc"))
- "r24k_fpu_iss")
+ "r24kf2_1_fpu_iss")
;; --------------------------------------------------------------
;; Bypass to Consumer
;; --------------------------------------------------------------
-;; r24k_fcvt_f2i->l/s base : 11 cycles
-;; r24k_fcvt_f2i->prefetch : 11 cycles
-(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_load")
-(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_prefetch")
-
-;; r24k_fxfer->l/s base : 5 cycles
-;; r24k_fxfer->prefetch : 5 cycles
-(define_bypass 5 "r24k_fxfer" "r24k_int_load")
-(define_bypass 5 "r24k_fxfer" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 5 "r24k_fxfer" "r24k_int_prefetch")
+;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
+;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
+
+;; r24kf2_1_fxfer->l/s base : 5 cycles
+;; r24kf2_1_fxfer->prefetch : 5 cycles
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
;; --------------------------------------------------------------
-;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
+;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
;; the unscaled timings
;; --------------------------------------------------------------
-(define_reservation "r24kx_fpu_iss" "r24k_iss+r24k_fpu_arith")
+(define_reservation "r24kf1_1_fpu_iss" "r24k_iss+r24k_fpu_arith")
;; fadd, fabs, fneg
-(define_insn_reservation "r24kx_fadd" 4
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fadd" 4
+ (and (eq_attr "cpu" "24kf1_1")
(eq_attr "type" "fadd,fabs,fneg"))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fmove, fcmove
-(define_insn_reservation "r24kx_fmove" 4
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fmove" 4
+ (and (eq_attr "cpu" "24kf1_1")
(eq_attr "type" "fmove,condmove"))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fload
-(define_insn_reservation "r24kx_fload" 3
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fload" 3
+ (and (eq_attr "cpu" "24kf1_1")
(eq_attr "type" "fpload,fpidxload"))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fstore
-(define_insn_reservation "r24kx_fstore" 1
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fstore" 1
+ (and (eq_attr "cpu" "24kf1_1")
(eq_attr "type" "fpstore"))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fmul, fmadd
-(define_insn_reservation "r24kx_fmul_sf" 4
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fmul_sf" 4
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
-(define_insn_reservation "r24kx_fmul_df" 5
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fmul_df" 5
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
- "r24kx_fpu_iss,r24k_fpu_arith")
+ "r24kf1_1_fpu_iss,r24k_fpu_arith")
;; fdiv, fsqrt, frsqrt
-(define_insn_reservation "r24kx_fdiv_sf" 17
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fdiv_sf" 17
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
- "r24kx_fpu_iss,(r24k_fpu_arith*13)")
+ "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)")
-(define_insn_reservation "r24kx_fdiv_df" 32
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fdiv_df" 32
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
- "r24kx_fpu_iss,(r24k_fpu_arith*28)")
+ "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)")
;; frsqrt
-(define_insn_reservation "r24kx_frsqrt_df" 35
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_frsqrt_df" 35
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
- "r24kx_fpu_iss,(r24k_fpu_arith*30)")
+ "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)")
;; fcmp
-(define_insn_reservation "r24kx_fcmp" 2
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcmp" 2
+ (and (eq_attr "cpu" "24kf1_1")
(eq_attr "type" "fcmp"))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
-(define_bypass 1 "r24kx_fcmp" "r24kx_fmove")
+(define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove")
;; fcvt (cvt.d.s, cvt.[sd].[wl])
-(define_insn_reservation "r24kx_fcvt_i2f_s2d" 4
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fcvt (cvt.s.d)
-(define_insn_reservation "r24kx_fcvt_s2d" 6
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcvt_s2d" 6
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "D2S")))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fcvt (cvt.[wl].[sd], etc)
-(define_insn_reservation "r24kx_fcvt_f2i" 5
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcvt_f2i" 5
+ (and (eq_attr "cpu" "24kf1_1")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "S2I,D2I")))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
-(define_insn_reservation "r24kx_fxfer" 2
- (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fxfer" 2
+ (and (eq_attr "cpu" "24kf1_1")
(eq_attr "type" "mfc,mtc"))
- "r24kx_fpu_iss")
+ "r24kf1_1_fpu_iss")
;; --------------------------------------------------------------
;; Bypass to Consumer
;; --------------------------------------------------------------
-;; r24kx_fcvt_f2i->l/s base : 6 cycles
-;; r24kx_fcvt_f2i->prefetch : 6 cycles
-(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_load")
-(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_prefetch")
-
-;; r24kx_fxfer->l/s base : 3 cycles
-;; r24kx_fxfer->prefetch : 3 cycles
-(define_bypass 3 "r24kx_fxfer" "r24k_int_load")
-(define_bypass 3 "r24kx_fxfer" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 3 "r24kx_fxfer" "r24k_int_prefetch")
+;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
+;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
+
+;; r24kf1_1_fxfer->l/s base : 3 cycles
+;; r24kf1_1_fxfer->prefetch : 3 cycles
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
;; xor, xori
(define_insn_reservation "r74k_int_arith" 2
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "arith,const,shift,slt,clz"))
"r74k_alu")
(define_insn_reservation "r74k_int_nop" 0
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "nop"))
"nothing")
(define_insn_reservation "r74k_int_cmove" 4
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "condmove"))
"r74k_agen*2")
;; MDU: fully pipelined multiplier
;; mult, madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
(define_insn_reservation "r74k_int_mult" 4
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "imul,imadd"))
"r74k_alu+r74k_mul")
;; mul - delivers result to general register in 7 cycles
(define_insn_reservation "r74k_int_mul3" 7
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "imul3"))
"r74k_alu+r74k_mul")
;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
(define_insn_reservation "r74k_int_mfhilo" 7
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "mfhilo"))
"r74k_alu+r74k_mul")
;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
(define_insn_reservation "r74k_int_mthilo" 7
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "mthilo"))
"r74k_alu+r74k_mul")
;; div - default to 50 cycles for 32bit operands. Faster for 8 bit,
;; but is tricky to identify.
(define_insn_reservation "r74k_int_div" 50
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "idiv"))
"r74k_alu+r74k_mul*50")
;; call
(define_insn_reservation "r74k_int_call" 1
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "call"))
"r74k_agen")
;; branch/jump
(define_insn_reservation "r74k_int_jump" 1
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "branch,jump"))
"r74k_agen")
;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
;; prefetch: prefetch, prefetchx
(define_insn_reservation "r74k_int_load" 3
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "load,prefetch,prefetchx"))
"r74k_agen")
;; stores
(define_insn_reservation "r74k_int_store" 1
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(and (eq_attr "type" "store")
(eq_attr "mode" "!unknown")))
"r74k_agen")
;; affects scheduling via log links, but not used here).
;;
(define_insn_reservation "r74k_unknown" 1
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "unknown"))
"r74k_alu")
(define_insn_reservation "r74k_multi" 10
- (and (eq_attr "cpu" "74kc,74kf,74kx")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
(eq_attr "type" "multi"))
"(r74k_alu+r74k_agen)*10")
;; Floating Point Instructions
;; --------------------------------------------------------------
-;; 74Kf has FPU at 1/2 speed of CPU; 74Kx is the name used by GCC for
-;; a version with 1:1 speed FPU.
+;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio.
;; fadd, fabs, fneg,
-(define_insn_reservation "r74kx_fadd" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fadd" 4
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fadd,fabs,fneg"))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fadd" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fadd" 8
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "fadd,fabs,fneg"))
"r74k_fpu_arith*2")
;; fmove, fcmove
-(define_insn_reservation "r74kx_fmove" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fmove" 4
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fmove"))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fmove" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fmove" 8
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "fmove"))
"r74k_fpu_arith*2")
;; fload
-(define_insn_reservation "r74kx_fload" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fload" 4
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fpload,fpidxload"))
"r74k_agen+r74k_fpu_ldst")
-(define_insn_reservation "r74kf_fload" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fload" 8
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "fpload,fpidxload"))
"r74k_agen+(r74k_fpu_ldst*2)")
;; fstore
-(define_insn_reservation "r74kx_fstore" 1
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fstore" 1
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fpstore,fpidxstore"))
"r74k_agen+r74k_fpu_ldst")
-(define_insn_reservation "r74kf_fstore" 2
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fstore" 2
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "fpstore,fpidxstore"))
"r74k_agen+(r74k_fpu_ldst*2)")
;; fmul, fmadd
-(define_insn_reservation "r74kx_fmul_sf" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fmul_sf" 4
+ (and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fmul_sf" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fmul_sf" 8
+ (and (eq_attr "cpu" "74kf2_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*2")
-(define_insn_reservation "r74kx_fmul_df" 5
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fmul_df" 5
+ (and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*2")
-(define_insn_reservation "r74kf_fmul_df" 10
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fmul_df" 10
+ (and (eq_attr "cpu" "74kf2_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*4")
;; fdiv, fsqrt
-(define_insn_reservation "r74kx_fdiv_sf" 17
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fdiv_sf" 17
+ (and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*14")
-(define_insn_reservation "r74kf_fdiv_sf" 34
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fdiv_sf" 34
+ (and (eq_attr "cpu" "74kf2_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*28")
-(define_insn_reservation "r74kx_fdiv_df" 32
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fdiv_df" 32
+ (and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*29")
-(define_insn_reservation "r74kf_fdiv_df" 64
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fdiv_df" 64
+ (and (eq_attr "cpu" "74kf2_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*58")
;; frsqrt
-(define_insn_reservation "r74kx_frsqrt_sf" 17
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_frsqrt_sf" 17
+ (and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*14")
-(define_insn_reservation "r74kf_frsqrt_sf" 34
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_frsqrt_sf" 34
+ (and (eq_attr "cpu" "74kf2_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*28")
-(define_insn_reservation "r74kx_frsqrt_df" 36
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_frsqrt_df" 36
+ (and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*31")
-(define_insn_reservation "r74kf_frsqrt_df" 72
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_frsqrt_df" 72
+ (and (eq_attr "cpu" "74kf2_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*62")
;; fcmp
-(define_insn_reservation "r74kx_fcmp" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fcmp" 4
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fcmp"))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fcmp" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fcmp" 8
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "fcmp"))
"r74k_fpu_arith*2")
;; fcvt
-(define_insn_reservation "r74kx_fcvt" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fcvt" 4
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fcvt"))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fcvt" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fcvt" 8
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "fcvt"))
"r74k_fpu_arith*2")
;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
-(define_insn_reservation "r74kx_fxfer_to_c1" 4
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "mtc"))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fxfer_to_c1" 8
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fxfer_to_c1" 8
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "mtc"))
"r74k_fpu_arith*2")
-(define_insn_reservation "r74kx_fxfer_from_c1" 1
- (and (eq_attr "cpu" "74kx")
+(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
+ (and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "mfc"))
"r74k_fpu_arith")
-(define_insn_reservation "r74kf_fxfer_from_c1" 2
- (and (eq_attr "cpu" "74kf")
+(define_insn_reservation "r74kf2_1_fxfer_from_c1" 2
+ (and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "mfc"))
"r74k_fpu_arith*2")
{ "4kec", PROCESSOR_4KC, 33 },
{ "4kem", PROCESSOR_4KC, 33 },
{ "4kep", PROCESSOR_4KP, 33 },
- { "24kc", PROCESSOR_24KC, 33 }, /* 24K no FPU */
- { "24kf", PROCESSOR_24KF, 33 }, /* 24K 1:2 FPU */
- { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
+
+ { "24kc", PROCESSOR_24KC, 33 },
+ { "24kf2_1", PROCESSOR_24KF2_1, 33 },
+ { "24kf", PROCESSOR_24KF2_1, 33 },
+ { "24kf1_1", PROCESSOR_24KF1_1, 33 },
+ { "24kfx", PROCESSOR_24KF1_1, 33 },
+ { "24kx", PROCESSOR_24KF1_1, 33 },
+
{ "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
- { "24kef", PROCESSOR_24KF, 33 },
- { "24kex", PROCESSOR_24KX, 33 },
- { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
- { "34kf", PROCESSOR_24KF, 33 },
- { "34kx", PROCESSOR_24KX, 33 },
- { "74kc", PROCESSOR_74KC, 33 },
- { "74kf", PROCESSOR_74KF, 33 },
- { "74kx", PROCESSOR_74KX, 33 },
+ { "24kef2_1", PROCESSOR_24KF2_1, 33 },
+ { "24kef", PROCESSOR_24KF2_1, 33 },
+ { "24kef1_1", PROCESSOR_24KF1_1, 33 },
+ { "24kefx", PROCESSOR_24KF1_1, 33 },
+ { "24kex", PROCESSOR_24KF1_1, 33 },
+
+ { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
+ { "34kf2_1", PROCESSOR_24KF2_1, 33 },
+ { "34kf", PROCESSOR_24KF2_1, 33 },
+ { "34kf1_1", PROCESSOR_24KF1_1, 33 },
+ { "34kfx", PROCESSOR_24KF1_1, 33 },
+ { "34kx", PROCESSOR_24KF1_1, 33 },
+
+ { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
+ { "74kf2_1", PROCESSOR_74KF2_1, 33 },
+ { "74kf", PROCESSOR_74KF2_1, 33 },
+ { "74kf1_1", PROCESSOR_74KF1_1, 33 },
+ { "74kfx", PROCESSOR_74KF1_1, 33 },
+ { "74kx", PROCESSOR_74KF1_1, 33 },
/* MIPS64 */
{ "5kc", PROCESSOR_5KC, 64 },
1, /* branch_cost */
4 /* memory_latency */
},
- { /* 24KF */
+ { /* 24KF2_1 */
COSTS_N_INSNS (8), /* fp_add */
COSTS_N_INSNS (8), /* fp_mult_sf */
COSTS_N_INSNS (10), /* fp_mult_df */
1, /* branch_cost */
4 /* memory_latency */
},
- { /* 24KX */
+ { /* 24KF1_1 */
COSTS_N_INSNS (4), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
COSTS_N_INSNS (5), /* fp_mult_df */
1, /* branch_cost */
4 /* memory_latency */
},
- { /* 74KF */
+ { /* 74KF2_1 */
COSTS_N_INSNS (8), /* fp_add */
COSTS_N_INSNS (8), /* fp_mult_sf */
COSTS_N_INSNS (10), /* fp_mult_df */
1, /* branch_cost */
4 /* memory_latency */
},
- { /* 74KX */
+ { /* 74KF1_1 */
COSTS_N_INSNS (4), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
COSTS_N_INSNS (5), /* fp_mult_df */
switch (mips_tune)
{
case PROCESSOR_74KC:
- case PROCESSOR_74KF:
- case PROCESSOR_74KX:
+ case PROCESSOR_74KF2_1:
+ case PROCESSOR_74KF1_1:
case PROCESSOR_R4130:
case PROCESSOR_R5400:
case PROCESSOR_R5500:
PROCESSOR_5KF,
PROCESSOR_20KC,
PROCESSOR_24KC,
- PROCESSOR_24KF,
- PROCESSOR_24KX,
+ PROCESSOR_24KF2_1,
+ PROCESSOR_24KF1_1,
PROCESSOR_74KC,
- PROCESSOR_74KF,
- PROCESSOR_74KX,
+ PROCESSOR_74KF2_1,
+ PROCESSOR_74KF1_1,
PROCESSOR_M4K,
PROCESSOR_R3900,
PROCESSOR_R6000,
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)
#define TUNE_74K (mips_tune == PROCESSOR_74KC \
- || mips_tune == PROCESSOR_74KF \
- || mips_tune == PROCESSOR_74KX)
+ || mips_tune == PROCESSOR_74KF2_1 \
+ || mips_tune == PROCESSOR_74KF1_1)
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf,24kx,74kc,74kf,74kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
@samp{4kec}, @samp{4kem}, @samp{4kep},
@samp{5kc}, @samp{5kf},
@samp{20kc},
-@samp{24kc}, @samp{24kf}, @samp{24kx},
-@samp{24kec}, @samp{24kef}, @samp{24kex},
-@samp{34kc}, @samp{34kf}, @samp{34kx},
-@samp{74kc}, @samp{74kf}, @samp{74kx},
+@samp{24kc}, @samp{24kf2_1}, @samp{24kf1_1},
+@samp{24kec}, @samp{24kef2_1}, @samp{24kef1_1},
+@samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1},
+@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1},
@samp{m4k},
@samp{orion},
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
(for example, @samp{-march=r2k}). Prefixes are optional, and
@samp{vr} may be written @samp{r}.
+Names of the form @samp{@var{n}f2_1} refer to processors with
+FPUs clocked at half the rate of the core. Names of the form
+@samp{@var{n}f1_1} refer to processors with FPUs clocked at the same
+rate as the core. For compatibility reasons, @samp{@var{n}f} is
+accepted as a synonym for @samp{@var{n}f2_1} while @samp{@var{n}x} and
+@samp{@var{b}fx} are accepted as synonyms for @samp{@var{n}f1_1}.
+
GCC defines two macros based on the value of this option. The first
is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
a string. The second has the form @samp{_MIPS_ARCH_@var{foo}},
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