void
optimization_options (level, size)
- int level;
+ int level ATTRIBUTE_UNUSED;
int size ATTRIBUTE_UNUSED;
{
}
if (((c >>= 1) & 1) != last_bit_value)
last_bit_value ^= 1, transitions++;
+ return transitions <= 1;
+ }
+ else if (GET_CODE (op) == CONST_DOUBLE
+ && (mode == VOIDmode || mode == DImode))
+ {
+ HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
+#if HOST_BITS_PER_WIDE_INT == 32
+ HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
+#endif
+ int i;
+ int last_bit_value;
+ int transitions = 0;
+
+ if ((low == 0
+#if HOST_BITS_PER_WIDE_INT == 32
+ && high == 0
+#endif
+ )
+ || (low == ~0
+#if HOST_BITS_PER_WIDE_INT == 32
+ && high == ~0
+#endif
+ ))
+ return 0;
+
+ last_bit_value = low & 1;
+
+ for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
+ if (((low >>= 1) & 1) != last_bit_value)
+ last_bit_value ^= 1, transitions++;
+
#if HOST_BITS_PER_WIDE_INT == 32
- /* Consider CONST_INT sign-extended. */
- transitions += (last_bit_value != 1);
+ if ((high & 1) != last_bit_value)
+ last_bit_value ^= 1, transitions++;
+
+ for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
+ if (((high >>= 1) & 1) != last_bit_value)
+ last_bit_value ^= 1, transitions++;
#endif
return transitions <= 1;
}
+ else
+ return 0;
+}
+
+/* Return 1 if the operand is a constant that is a PowerPC64 mask.
+ It is if there are no more than two 1->0 or 0->1 transitions.
+ Reject all ones and all zeros, since these should have been optimized
+ away and confuse the making of MB and ME. */
+
+int
+rldic_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+{
+ if (GET_CODE (op) == CONST_INT)
+ {
+ HOST_WIDE_INT c = INTVAL (op);
+ int i;
+ int last_bit_value;
+ int transitions = 0;
+
+ if (c == 0 || c == ~0)
+ return 0;
+
+ last_bit_value = c & 1;
+
+ for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
+ if (((c >>= 1) & 1) != last_bit_value)
+ last_bit_value ^= 1, transitions++;
+
+ return transitions <= 2;
+ }
else if (GET_CODE (op) == CONST_DOUBLE
&& (mode == VOIDmode || mode == DImode))
{
last_bit_value ^= 1, transitions++;
#endif
- return transitions <= 1;
+ return transitions <= 2;
}
else
return 0;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
int count = XVECLEN (op, 0);
- int dest_regno;
+ unsigned int dest_regno;
rtx src_addr;
int i;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
int count = XVECLEN (op, 0) - 1;
- int src_regno;
+ unsigned int src_regno;
rtx dest_addr;
int i;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
int count = XVECLEN (op, 0);
- int dest_regno;
+ unsigned int dest_regno;
rtx src_addr;
- int base_regno;
+ unsigned int base_regno;
HOST_WIDE_INT offset;
int i;
src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
if (dest_regno > 31
- || count != 32 - dest_regno)
+ || count != 32 - (int) dest_regno)
return 0;
if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr))
enum machine_mode mode ATTRIBUTE_UNUSED;
{
int count = XVECLEN (op, 0);
- int src_regno;
+ unsigned int src_regno;
rtx dest_addr;
- int base_regno;
+ unsigned int base_regno;
HOST_WIDE_INT offset;
int i;
dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
if (src_regno > 31
- || count != 32 - src_regno)
+ || count != 32 - (int) src_regno)
return 0;
if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr))
register rtx shiftop;
register rtx andop;
{
- int shift_mask = (~0 << INTVAL (shiftop));
+ unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
+
+ shift_mask <<= INTVAL (shiftop);
return (INTVAL (andop) & ~shift_mask) == 0;
}
shift_mask >>= INTVAL (shiftop);
- return (INTVAL (andop) & ~ shift_mask) == 0;
+ return (INTVAL (andop) & ~shift_mask) == 0;
+}
+
+/* Return 1 if ANDOP is a mask that has no bits on that are not in the
+ mask required to convert the result of a rotate insn into a shift
+ left insn of SHIFTOP bits. */
+
+int
+includes_lshift64_p (shiftop, andop)
+ register rtx shiftop;
+ register rtx andop;
+{
+#if HOST_BITS_PER_WIDE_INT == 64
+ unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
+
+ shift_mask <<= INTVAL (shiftop);
+
+ return (INTVAL (andop) & ~shift_mask) == 0;
+#else
+ unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0;
+ unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0;
+
+ shift_mask_low <<= INTVAL (shiftop);
+
+ if (INTVAL (shiftop) > 32)
+ shift_mask_high <<= (INTVAL (shiftop) - 32);
+
+ if (GET_CODE (andop) == CONST_INT)
+ return (INTVAL (andop) & ~shift_mask_low) == 0;
+ else
+ return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0
+ && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0);
+#endif
}
/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
register rtx addr1;
register rtx addr2;
{
- int reg1;
+ unsigned int reg1;
int offset1;
/* Extract an offset (if used) from the first addr. */
return;
case 'b':
- /* Low-order 16 bits of constant, unsigned. */
- if (! INT_P (x))
- output_operand_lossage ("invalid %%b value");
-
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
+ /* If constant, low-order 16 bits of constant, unsigned.
+ Otherwise, write normally. */
+ if (INT_P (x))
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
+ else
+ print_operand (file, x, 0);
return;
case 'B':
else
putc ('m', file);
return;
-
+
case 'h':
/* If constant, output low-order five bits. Otherwise,
write normally. */
constant. */
if (! INT_P (x))
output_operand_lossage ("invalid %%k value");
-
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
+ else
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
return;
case 'K':
/* Write the number of elements in the vector times 4. */
if (GET_CODE (x) != PARALLEL)
output_operand_lossage ("invalid %%N value");
-
- fprintf (file, "%d", XVECLEN (x, 0) * 4);
+ else
+ fprintf (file, "%d", XVECLEN (x, 0) * 4);
return;
case 'O':
/* Similar, but subtract 1 first. */
if (GET_CODE (x) != PARALLEL)
output_operand_lossage ("invalid %%O value");
-
- fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
+ else
+ fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
return;
case 'p':
if (! INT_P (x)
|| (i = exact_log2 (INT_LOWPART (x))) < 0)
output_operand_lossage ("invalid %%p value");
-
- fprintf (file, "%d", i);
+ else
+ fprintf (file, "%d", i);
return;
case 'P':
if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
|| REGNO (XEXP (x, 0)) >= 32)
output_operand_lossage ("invalid %%P value");
-
- fprintf (file, "%d", REGNO (XEXP (x, 0)));
+ else
+ fprintf (file, "%d", REGNO (XEXP (x, 0)));
return;
case 'q':
/* Low 5 bits of 32 - value */
if (! INT_P (x))
output_operand_lossage ("invalid %%s value");
-
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
+ else
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
return;
case 'S':
if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
&& REGNO (x) != COUNT_REGISTER_REGNUM))
output_operand_lossage ("invalid %%T value");
-
- if (REGNO (x) == LINK_REGISTER_REGNUM)
+ else if (REGNO (x) == LINK_REGISTER_REGNUM)
fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
else
fputs ("ctr", file);
/* High-order 16 bits of constant for use in unsigned operand. */
if (! INT_P (x))
output_operand_lossage ("invalid %%u value");
-
- fprintf (file, HOST_WIDE_INT_PRINT_HEX,
- (INT_LOWPART (x) >> 16) & 0xffff);
+ else
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX,
+ (INT_LOWPART (x) >> 16) & 0xffff);
return;
case 'v':
/* High-order 16 bits of constant for use in signed operand. */
if (! INT_P (x))
output_operand_lossage ("invalid %%v value");
+ else
+ {
+ int value = (INT_LOWPART (x) >> 16) & 0xffff;
- {
- int value = (INT_LOWPART (x) >> 16) & 0xffff;
-
- /* Solaris assembler doesn't like lis 0,0x8000 */
- if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
- fprintf (file, "%d", value | (~0 << 16));
- else
- fprintf (file, "0x%x", value);
- return;
- }
+ /* Solaris assembler doesn't like lis 0,0x8000 */
+ if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
+ fprintf (file, "%d", value | (~0 << 16));
+ else
+ fprintf (file, "0x%x", value);
+ return;
+ }
case 'U':
/* Print `u' if this has an auto-increment or auto-decrement. */
return;
case 'W':
- /* If constant, low-order 16 bits of constant, unsigned.
- Otherwise, write normally. */
- if (INT_P (x))
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
+ /* MB value for a PowerPC64 rldic operand. */
+ if (! rldic_operand (x, VOIDmode))
+ output_operand_lossage ("invalid %%W value");
+
+ val = (GET_CODE (x) == CONST_INT
+ ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
+
+ if (val < 0)
+ i = -1;
else
- print_operand (file, x, 0);
+ for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
+ if ((val <<= 1) < 0)
+ break;
+
+#if HOST_BITS_PER_WIDE_INT == 32
+ if (GET_CODE (x) == CONST_INT && i >= 0)
+ i += 32; /* zero-extend high-part was all 0's */
+ else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
+ {
+ val = CONST_DOUBLE_LOW (x);
+
+ if (val == 0)
+ abort();
+ else if (val < 0)
+ --i;
+ else
+ for ( ; i < 64; i++)
+ if ((val <<= 1) < 0)
+ break;
+ }
+#endif
+
+ fprintf (file, "%d", i + 1);
return;
case 'X':
although IBM appears to be using 13. There is no official value
for Chill, so we've choosen 44 pseudo-randomly. */
if (! strcmp (language_string, "GNU C")
- || ! strcmp (language_string, "GNU Obj-C"))
+ || ! strcmp (language_string, "GNU Objective-C"))
i = 0;
else if (! strcmp (language_string, "GNU F77"))
i = 1;
else if (GET_MODE (x) == VOIDmode
&& (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
{
- HOST_WIDE_INT low;
+ unsigned HOST_WIDE_INT low;
HOST_WIDE_INT high;
if (GET_CODE (x) == CONST_DOUBLE)
#if HOST_BITS_PER_WIDE_INT == 32
{
low = INTVAL (x);
- high = (low < 0) ? ~0 : 0;
+ high = (low & 0x80000000u) ? ~0 : 0;
}
#else
{
- low = INTVAL (x) & 0xffffffff;
+ low = INTVAL (x) & 0xffffffffu;
high = (HOST_WIDE_INT) INTVAL (x) >> 32;
}
#endif
FAIL;
}")
-(define_insn ""
+(define_insn "*ashldi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"sld%I2 %0,%1,%H2"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*ashldi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))]
"")
-(define_insn ""
+(define_insn "*ashldi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))]
"")
-(define_insn ""
+(define_insn "*ashldi3_internal4"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:DI 3 "mask64_operand" "S")))]
- "((GET_CODE (operands[3]) == CONST_INT
- ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
- "rldic %0,%1,%H2,%S3")
+ (match_operand:DI 3 "rldic_operand" "n")))]
+ "includes_lshift64_p (operands[2], operands[3])"
+ "rldic %0,%1,%H2,%W3")
-(define_insn ""
+(define_insn "ashldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "mask64_operand" "S,S"))
+ (match_operand:DI 3 "rldic_operand" "n,n"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r,r"))]
- "((GET_CODE (operands[3]) == CONST_INT
- ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+ "includes_lshift64_p (operands[2], operands[3])"
"@
- rldic. %0,%1,%H2,%S3
+ rldic. %4,%1,%H2,%W3
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "const_int_operand" ""))
- (match_operand:DI 3 "mask64_operand" ""))
+ (match_operand:DI 3 "rldic_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 4 ""))]
- "((GET_CODE (operands[3]) == CONST_INT
- ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1
- && reload_completed"
+ "includes_lshift64_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 4)
(and:DI (ashift:DI (match_dup 1) (match_dup 2))
- (match_dup 3)))
+ (match_dup 3)))
(set (match_dup 0)
(compare:CC (match_dup 4)
(const_int 0)))]
"")
-(define_insn ""
+(define_insn "*ashldi3_internal6"
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "mask64_operand" "S,S"))
+ (match_operand:DI 3 "rldic_operand" "n,n"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "((GET_CODE (operands[3]) == CONST_INT
- ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+ "includes_lshift64_p (operands[2], operands[3])"
"@
- rldic. %0,%1,%H2,%S3
+ rldic. %0,%1,%H2,%W3
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "const_int_operand" ""))
- (match_operand:DI 3 "mask64_operand" ""))
+ (match_operand:DI 3 "rldic_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "((GET_CODE (operands[3]) == CONST_INT
- ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1
- && reload_completed"
+ "includes_lshift64_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 0)
- (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+ (match_dup 3)))
(set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
FAIL;
}")
-(define_insn ""
+(define_insn "*lshrdi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
"srd%I2 %0,%1,%H2")
-(define_insn ""
+(define_insn "*lshrdi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))]
"")
-(define_insn ""
+(define_insn "*lshrdi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
FAIL;
}")
-(define_insn ""
+(define_insn "*ashrdi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
"srad%I2 %0,%1,%H2")
-(define_insn ""
+(define_insn "*ashrdi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))]
"")
-(define_insn ""
+(define_insn "*ashrdi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
emit_insn (gen_iordi3 (tmp, operands[1],
GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
}
- else if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ else
{
value = CONST_DOUBLE_LOW (operands[2]);
emit_insn (gen_iordi3 (tmp, operands[1],
& (~ (HOST_WIDE_INT) 0xffff),
0, DImode)));
}
+
emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
DONE;
}
emit_insn (gen_xordi3 (tmp, operands[1],
GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
}
- else if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ else
{
value = CONST_DOUBLE_LOW (operands[2]);
emit_insn (gen_xordi3 (tmp, operands[1],
& (~ (HOST_WIDE_INT) 0xffff),
0, DImode)));
}
+
emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
DONE;
}
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
""
- "{cmpl%I2|cmplw%I2} %0,%1,%W2"
+ "{cmpl%I2|cmplw%I2} %0,%1,%b2"
[(set_attr "type" "compare")])
(define_insn "*cmpdi_internal2"
(compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
""
- "cmpld%I2 %0,%1,%W2"
+ "cmpld%I2 %0,%1,%b2"
[(set_attr "type" "compare")])
;; The following two insns don't exist as single insns, but if we provide
OSDN Git Service
