(andsi3, iorsi3, xorsi3): Make the constraints match

the real machine (the predicate still is more general in order
to optimize bitfields at the expense of not CSE'ing large
constants used in logical ops, and making reload load it into
a scratch register).  Don't use $1 as a temporary register any
more.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@1217 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 730d624..8b7c228 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1148,52 +1148,17 @@ move\\t%0,%z4\\n\\
 ;;  ....................
 ;;
 
-;; Be more liberal in allowing logical operations than the machine actually
-;; supports.  This causes better code to be generated for bitfields, since
-;; the optimizer can fold things together, at the expense of not moving the
-;; constant out of loops.
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (and:SI (match_operand:SI 1 "arith32_operand" "dKIM")
-               (match_operand:SI 2 "arith32_operand" "dKIM")))]
-  ""
-  "
-{
-  extern rtx gen_andsi3_internal2 ();
-
-  /* Canonlicalize */
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx temp;
-
-      if (GET_CODE (operands[2]) == CONST_INT)
-       {
-         emit_move_insn (operands[0],
-                         gen_rtx (CONST_INT, VOIDmode,
-                                  INTVAL (operands[1]) & INTVAL (operands[2])));
-         DONE;
-       }
-
-      temp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = temp;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
-    {
-      emit_insn (gen_andsi3_internal2 (operands[0],
-                                      operands[1],
-                                      operands[2],
-                                      gen_reg_rtx (SImode)));
-      DONE;
-    }
-}")
-
-(define_insn "andsi3_internal1"
+;; Be more liberal in allowing logical operations than the machine
+;; actually supports, until the reload phase forces the large integers
+;; into registers.  This causes better code to be generated for
+;; bitfields, since the optimizer can fold things together, at the
+;; expense of not CSE'ing or moving the constant out of loops, and
+;; having reload load the constant into a scratch register.
+
+(define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-       (and:SI (match_operand:SI 1 "register_operand" "d,d")
-               (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+       (and:SI (match_operand:SI 1 "arith32_operand" "%d,d")
+               (match_operand:SI 2 "arith32_operand" "d,K")))]
   ""
   "@
    and\\t%0,%1,%2
@@ -1202,49 +1167,6 @@ move\\t%0,%z4\\n\\
    (set_attr "mode"    "SI")
    (set_attr "length"  "1")])
 
-(define_insn "andsi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-       (and:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
-               (match_operand:SI 2 "arith32_operand" "d,K,I,M")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
-  ""
-  "@
-   and\\t%0,%1,%2
-   andi\\t%0,%1,%x2
-   li\\t%3,%X2\\t\\t# %2\;and\\t%0,%1,%3
-   li\\t%3,%X2\\t\\t# %2\;and\\t%0,%1,%3"
-  [(set_attr "type"    "arith,arith,multi,multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "1,1,2,3")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-       (and:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "lui_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !TARGET_DEBUG_D_MODE"
-
-  [(set (match_dup 3) (match_dup 2))
-   (set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-       (and:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "large_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !TARGET_DEBUG_D_MODE"
-
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
-   (set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))]
-  "
-{
-  int val = INTVAL (operands[2]);
-  operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
-  operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
-}")
-
 (define_insn "anddi3"
   [(set (match_operand:DI 0 "register_operand" "=d")
        (and:DI (match_operand:DI 1 "register_operand" "d")
@@ -1268,47 +1190,10 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
   "")
 
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (ior:SI (match_operand:SI 1 "arith32_operand" "dKIM")
-               (match_operand:SI 2 "arith32_operand" "dKIM")))]
-  ""
-  "
-{
-  extern rtx gen_iorsi3_internal2 ();
-
-  /* Canonlicalize */
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx temp;
-
-      if (GET_CODE (operands[2]) == CONST_INT)
-       {
-         emit_move_insn (operands[0],
-                         gen_rtx (CONST_INT, VOIDmode,
-                                  INTVAL (operands[1]) | INTVAL (operands[2])));
-         DONE;
-       }
-
-      temp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = temp;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
-    {
-      emit_insn (gen_iorsi3_internal2 (operands[0],
-                                      operands[1],
-                                      operands[2],
-                                      gen_reg_rtx (SImode)));
-      DONE;
-    }
-}")
-
-(define_insn "iorsi3_internal1"
+(define_insn "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-       (ior:SI (match_operand:SI 1 "register_operand" "d,d")
-               (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+       (ior:SI (match_operand:SI 1 "arith32_operand" "%d,d")
+               (match_operand:SI 2 "arith32_operand" "d,K")))]
   ""
   "@
    or\\t%0,%1,%2
@@ -1317,49 +1202,6 @@ move\\t%0,%z4\\n\\
    (set_attr "mode"    "SI")
    (set_attr "length"  "1")])
 
-(define_insn "iorsi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-       (ior:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
-               (match_operand:SI 2 "arith32_operand" "d,K,I,M")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
-  ""
-  "@
-   or\\t%0,%1,%2
-   ori\\t%0,%1,%x2
-   li\\t%3,%X2\\t\\t# %2\;or\\t%0,%1,%3
-   li\\t%3,%X2\\t\\t# %2\;or\\t%0,%1,%3"
-  [(set_attr "type"    "arith,arith,multi,multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "1,1,2,3")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-       (ior:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "lui_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !TARGET_DEBUG_D_MODE"
-
-  [(set (match_dup 3) (match_dup 2))
-   (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-       (ior:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "large_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !TARGET_DEBUG_D_MODE"
-
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
-   (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
-  "
-{
-  int val = INTVAL (operands[2]);
-  operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
-  operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
-}")
-
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "register_operand" "=d")
        (ior:DI (match_operand:DI 1 "register_operand" "d")
@@ -1383,47 +1225,10 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
   "")
 
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (xor:SI (match_operand:SI 1 "arith32_operand" "dKIM")
-               (match_operand:SI 2 "arith32_operand" "dKIM")))]
-  ""
-  "
-{
-  extern rtx gen_xorsi3_internal2 ();
-
-  /* Canonlicalize */
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx temp;
-
-      if (GET_CODE (operands[2]) == CONST_INT)
-       {
-         emit_move_insn (operands[0],
-                         gen_rtx (CONST_INT, VOIDmode,
-                                  INTVAL (operands[1]) ^ INTVAL (operands[2])));
-         DONE;
-       }
-
-      temp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = temp;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
-    {
-      emit_insn (gen_xorsi3_internal2 (operands[0],
-                                      operands[1],
-                                      operands[2],
-                                      gen_reg_rtx (SImode)));
-      DONE;
-    }
-}")
-
-(define_insn "xorsi3_internal1"
+(define_insn "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-       (xor:SI (match_operand:SI 1 "register_operand" "d,d")
-               (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+       (xor:SI (match_operand:SI 1 "arith32_operand" "%d,d")
+               (match_operand:SI 2 "arith32_operand" "d,K")))]
   ""
   "@
    xor\\t%0,%1,%2
@@ -1432,50 +1237,6 @@ move\\t%0,%z4\\n\\
    (set_attr "mode"    "SI")
    (set_attr "length"  "1")])
 
-(define_insn "xorsi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-       (xor:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
-               (match_operand:SI 2 "arith32_operand" "d,K,I,M")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
-  ""
-  "@
-   xor\\t%0,%1,%2
-   xori\\t%0,%1,%x2
-   li\\t%3,%X2\\t\\t# %2\;xor\\t%0,%1,%3
-   li\\t%3,%X2\\t\\t# %2\;xor\\t%0,%1,%3"
-  [(set_attr "type"    "arith,arith,multi,multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "1,1,2,3")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-       (xor:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "lui_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !TARGET_DEBUG_D_MODE"
-
-  [(set (match_dup 3) (match_dup 2))
-   (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-       (xor:SI (match_operand:SI 1 "register_operand" "")
-               (match_operand:SI 2 "large_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !TARGET_DEBUG_D_MODE"
-
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
-   (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))]
-  "
-{
-  int val = INTVAL (operands[2]);
-  operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
-  operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
-}")
-
-
 (define_insn "xordi3"
   [(set (match_operand:DI 0 "register_operand" "=d")
        (xor:DI (match_operand:DI 1 "register_operand" "d")