* i386.md (prefetch): Fix for 64bit mode.

	(prefetch_sse_rex, prefetch_3dnow_rex): New patterns.

	* i386.md (movss, movsd): Use xorps/xorpd for Athlon.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@55481 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 24e5c1e..e326efc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Tue Jul 16 12:22:44 CEST 2002  Jan Hubicka  <jh@suse.cz>
+
+       * i386.md (prefetch): Fix for 64bit mode.
+       (prefetch_sse_rex, prefetch_3dnow_rex): New patterns.
+
+       * i386.md (movss, movsd): Use xorps/xorpd for Athlon.
+
 2002-07-16  Marek Michalkiewicz  <marekm@amelek.gda.pl>
 
        * hard-reg-set.h (TEST_HARD_REG_BIT): Return 1 if the bit is set.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index d75ddee..ccfa57b 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2129,7 +2129,7 @@
     case 4:
       return "mov{l}\t{%1, %0|%0, %1}";
     case 5:
-      if (TARGET_SSE2)
+      if (TARGET_SSE2 && !TARGET_ATHLON)
        return "pxor\t%0, %0";
       else
        return "xorps\t%0, %0";
@@ -2315,7 +2315,10 @@
     case 4:
       return "#";
     case 5:
-      return "pxor\t%0, %0";
+      if (TARGET_ATHLON)
+        return "xorpd\t%0, %0";
+      else
+        return "pxor\t%0, %0";
     case 6:
       if (TARGET_PARTIAL_REG_DEPENDENCY)
        return "movapd\t{%1, %0|%0, %1}";
@@ -2374,7 +2377,10 @@
       return "#";
 
     case 5:
-      return "pxor\t%0, %0";
+      if (TARGET_ATHLON)
+        return "xorpd\t%0, %0";
+      else
+        return "pxor\t%0, %0";
     case 6:
       if (TARGET_PARTIAL_REG_DEPENDENCY)
        return "movapd\t{%1, %0|%0, %1}";
@@ -20015,7 +20021,7 @@
    (set_attr "mode" "TI")])
 
 (define_expand "prefetch"
-  [(prefetch (match_operand:SI 0 "address_operand" "")
+  [(prefetch (match_operand 0 "address_operand" "")
             (match_operand:SI 1 "const_int_operand" "")
             (match_operand:SI 2 "const_int_operand" ""))]
   "TARGET_PREFETCH_SSE || TARGET_3DNOW"
@@ -20027,6 +20033,8 @@
     abort ();
   if (locality < 0 || locality > 3)
     abort ();
+  if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
+    abort ();
 
   /* Use 3dNOW prefetch in case we are asking for write prefetch not
      suported by SSE counterpart or the SSE prefetch is not available
@@ -20042,7 +20050,26 @@
   [(prefetch (match_operand:SI 0 "address_operand" "p")
             (const_int 0)
             (match_operand:SI 1 "const_int_operand" ""))]
-  "TARGET_PREFETCH_SSE"
+  "TARGET_PREFETCH_SSE && !TARGET_64BIT"
+{
+  static const char * const patterns[4] = {
+   "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
+  };
+
+  int locality = INTVAL (operands[1]);
+  if (locality < 0 || locality > 3)
+    abort ();
+
+  return patterns[locality];  
+}
+  [(set_attr "type" "sse")
+   (set_attr "memory" "none")])
+
+(define_insn "*prefetch_sse_rex"
+  [(prefetch (match_operand:DI 0 "address_operand" "p")
+            (const_int 0)
+            (match_operand:SI 1 "const_int_operand" ""))]
+  "TARGET_PREFETCH_SSE && TARGET_64BIT"
 {
   static const char * const patterns[4] = {
    "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
@@ -20061,7 +20088,21 @@
   [(prefetch (match_operand:SI 0 "address_operand" "p")
             (match_operand:SI 1 "const_int_operand" "n")
             (const_int 3))]
-  "TARGET_3DNOW"
+  "TARGET_3DNOW && !TARGET_64BIT"
+{
+  if (INTVAL (operands[1]) == 0)
+    return "prefetch\t%a0";
+  else
+    return "prefetchw\t%a0";
+}
+  [(set_attr "type" "mmx")
+   (set_attr "memory" "none")])
+
+(define_insn "*prefetch_3dnow_rex"
+  [(prefetch (match_operand:DI 0 "address_operand" "p")
+            (match_operand:SI 1 "const_int_operand" "n")
+            (const_int 3))]
+  "TARGET_3DNOW && TARGET_64BIT"
 {
   if (INTVAL (operands[1]) == 0)
     return "prefetch\t%a0";