* config/h8300/h8300.md (4 anonymous patterns): New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@46554 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8098174..23f0e1e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2001-10-26  Kazu Hirata  <kazu@hxi.com>
 
+       * config/h8300/h8300.md (4 anonymous patterns): New.
+
+2001-10-26  Kazu Hirata  <kazu@hxi.com>
+
        * config/h8300/h8300.c (get_shift_alg): Clean up.  Return the
        algorithm through the shift_info structure.
        (emit_a_shift): Update the use of get_shift_alg.

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 8b6b39a..6d44305 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -2289,3 +2289,69 @@
   [(set_attr "cc" "clobber")
    (set_attr "length" "6")
    (set_attr "adjust_length" "no")])
+\f
+;; -----------------------------------------------------------------
+;; COMBINE PATTERNS
+;; -----------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (ior:HI
+           (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+           (match_operand:HI 2 "register_operand" "0")))]
+  "REGNO (operands[0]) != REGNO (operands[1])"
+  "or\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (ior:SI
+           (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+           (match_operand:SI 2 "register_operand" "0")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+    && (REGNO (operands[0]) != REGNO (operands[1]))"
+  "or.w\\t%T1,%f0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (ior:SI
+           (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+           (match_operand:SI 2 "register_operand" "0")))]
+  "REGNO (operands[0]) != REGNO (operands[1])"
+  "or\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+        (xor:HI
+           (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+           (match_operand:HI 2 "register_operand" "0")))]
+  "REGNO (operands[0]) != REGNO (operands[1])"
+  "xor\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (xor:SI
+           (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+           (match_operand:SI 2 "register_operand" "0")))]
+  "(TARGET_H8300H || TARGET_H8300S)
+    && (REGNO (operands[0]) != REGNO (operands[1]))"
+  "xor.w\\t%T1,%f0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (xor:SI
+           (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+           (match_operand:SI 2 "register_operand" "0")))]
+  "REGNO (operands[0]) != REGNO (operands[1])"
+  "xor\\t%X1,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])