* config/m68hc11/m68hc11.md ("negsi2"): Optimize inline case.

	("neghi2"): Tighten constraints.
	("one_cmplsi2"): Optimize and simplify split.
	* config/m68hc11/larith.asm (__negsi2): Likewise for library.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@50847 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 288c322..66c6da7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2002-03-15  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
 
+       * config/m68hc11/m68hc11.md ("negsi2"): Optimize inline case.
+       ("neghi2"): Tighten constraints.
+       ("one_cmplsi2"): Optimize and simplify split.
+       * config/m68hc11/larith.asm (__negsi2): Likewise for library.
+
+2002-03-15  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
        * config/m68hc11/m68hc11.md ("logicalsi3_zexthi"): Fix constraints
        and split of AND operation to clear the upper bits.
        ("*logicalsi3_zextqi"): Likewise.

diff --git a/gcc/config/m68hc11/larith.asm b/gcc/config/m68hc11/larith.asm
index b39d81a..94e1596 100644 (file)
--- a/gcc/config/m68hc11/larith.asm
+++ b/gcc/config/m68hc11/larith.asm
@@ -443,13 +443,14 @@ ___notdi2:
 ___negsi2:
        comb
        coma
-       addd    #1
        xgdx
-       eorb    #0xFF
-       eora    #0xFF
-       adcb    #0
-       adca    #0
+       comb
+       coma
+       inx
        xgdx
+       bne     done
+       inx
+done:
        rts
 #endif
 

diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index 306053f..6f9c73b 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -4206,26 +4206,31 @@
 
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=D")
-       (neg:SI (match_operand:SI 1 "register_operand" "0")))]
+       (neg:SI (match_operand:SI 1 "general_operand" "0")))]
   ""
   "*
 {
+  rtx ops[1];
+
   CC_STATUS_INIT;
 
   /* With -Os or without -O, use a special library call.  */
   if (optimize_size || optimize == 0)
     return \"bsr\\t___negsi2\";
 
-  /* 32-bit complement and add 1.  The comb/coma set the carry and they
-     are smaller (use it for low-part).  The eorb/eora leave the carry
-     unchanged but are bigger (use it for high-part).  */
-  output_asm_insn (\"comb\\n\\tcoma\\n\\taddd\\t#1\\n\\txgdx\", operands);
-  output_asm_insn (\"eorb\\t#0xFF\\n\\teora\\t#0xFF\", operands);
-  return \"adcb\\t#0\\n\\tadca\\t#0\\n\\txgdx\";
+  ops[0] = gen_label_rtx ();
+
+  /* 32-bit complement and add 1.  */
+  output_asm_insn (\"comb\\n\\tcoma\\n\\txgdx\", operands);
+  output_asm_insn (\"comb\\n\\tcoma\\n\\tinx\\n\\txgdx\", operands);
+  output_asm_insn (\"bne\\t%l0\", ops);
+  output_asm_insn (\"inx\", operands);
+  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[0]));
+  return \"\";
 }")
 
 (define_insn "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=d,d,*A")
+  [(set (match_operand:HI 0 "register_operand" "=d,d,x*y")
        (neg:HI (match_operand:HI 1 "general_operand" "0,!duim,0")))]
   ""
   "@
@@ -4255,57 +4260,62 @@
    DONE;")
 
 (define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "non_push_operand" "=D")
-       (not:SI (match_operand:SI 1 "general_operand" "0")))]
+  [(set (match_operand:SI 0 "non_push_operand" "=D,m,!u")
+       (not:SI (match_operand:SI 1 "general_operand" "0,m,0")))
+   (clobber (match_scratch:HI 2 "=X,d,X"))]
   ""
-  "bsr\\t___one_cmplsi2")
+  "@
+   bsr\\t___one_cmplsi2
+   #
+   #")
 
 (define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "non_push_operand" "=d,m,!u,*A")
+  [(set (match_operand:HI 0 "non_push_operand" "=d,m,*A,u")
        (not:HI (match_operand:HI 1 "general_operand" "0,0,0,0")))]
   ""
   "@
    comb\\n\\tcoma
    com\\t%b0\\n\\tcom\\t%h0
-   com\\t%b0\\n\\tcom\\t%h0
-   #")
+   #
+   com\\t%b0\\n\\tcom\\t%h0")
 
 (define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "non_push_operand" "=d,m,!u,!*A")
+  [(set (match_operand:QI 0 "non_push_operand" "=d,m,*A,u")
        (not:QI (match_operand:QI 1 "general_operand" "0,0,0,0")))]
   ""
   "@
    comb
    com\\t%b0
-   com\\t%b0
-   #")
+   #
+   com\\t%b0")
 
 (define_split /* "*one_cmplsi2" */
-  [(set (match_operand:SI 0 "non_push_operand" "=Dum")
-       (not:SI (match_operand:SI 1 "non_push_operand" "0")))]
+  [(set (match_operand:SI 0 "non_push_operand" "")
+       (not:SI (match_dup 0)))
+   (clobber (match_scratch:HI 1 ""))]
   "z_replacement_completed == 2
-   && (!D_REG_P (operands[0]) || (optimize && optimize_size == 0))"
-  [(set (reg:HI D_REGNUM) (not:HI (reg:HI D_REGNUM)))
-   (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM))
-              (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))])
-   (set (reg:HI D_REGNUM) (not:HI (reg:HI D_REGNUM)))
-   (parallel [(set (reg:HI X_REGNUM) (reg:HI D_REGNUM))
-              (set (reg:HI D_REGNUM) (reg:HI X_REGNUM))])]
-  "
-{
-  /* The result pattern only works for D register.
-     Generate 2 one_cmplhi2 instructions.  */
-  if (!D_REG_P (operands[0]))
-    {
-      rtx ops[2];
+   && (!X_REG_P (operands[0]) || (optimize && optimize_size == 0))"
+  [(set (match_dup 2) (not:HI (match_dup 2)))
+   (set (match_dup 3) (not:HI (match_dup 3)))]
+  "operands[2] = m68hc11_gen_lowpart (HImode, operands[0]);
+   operands[3] = m68hc11_gen_highpart (HImode, operands[0]);")
 
-      ops[0] = m68hc11_gen_lowpart (HImode, operands[0]);
-      ops[1] = m68hc11_gen_highpart (HImode, operands[0]);
-      emit_insn (gen_one_cmplhi2 (ops[0], ops[0]));
-      emit_insn (gen_one_cmplhi2 (ops[1], ops[1]));
-      DONE;
-    }
-}")
+(define_split /* "*one_cmplsi2" */
+  [(set (match_operand:SI 0 "non_push_operand" "")
+       (not:SI (match_operand:SI 1 "non_push_operand" "")))
+   (clobber (match_operand:HI 2 "d_register_operand" ""))]
+  "z_replacement_completed == 2
+   && (!X_REG_P (operands[0]) || (optimize && optimize_size == 0))"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 2) (not:HI (match_dup 2)))
+   (set (match_dup 4) (match_dup 2))
+   (set (match_dup 2) (match_dup 5))
+   (set (match_dup 2) (not:HI (match_dup 2)))
+   (set (match_dup 6) (match_dup 2))]
+  "operands[3] = m68hc11_gen_lowpart (HImode, operands[1]);
+   operands[5] = m68hc11_gen_highpart (HImode, operands[1]);
+   operands[4] = m68hc11_gen_lowpart (HImode, operands[0]);
+   operands[6] = m68hc11_gen_highpart (HImode, operands[0]);")
 
 ;;--------------------------------------------------------------------
 ;;- arithmetic shifts