--- /dev/null
+/* Definitions of target machine for GNU compiler. AT&T we32000 version.
+ Contributed by John Wehle (john@feith1.uucp)
+ Copyright (C) 1991-1992 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+
+/* Names to predefine in the preprocessor for this target machine. */
+
+#define CPP_PREDEFINES "-Dwe32000 -Du3b -Dunix"
+
+/* Print subsidiary information on the compiler version in use. */
+
+#define TARGET_VERSION fprintf (stderr, " (we32000)");
+
+/* Run-time compilation parameters selecting different hardware subsets. */
+
+extern int target_flags;
+
+/* Macros used in the machine description to test the flags. */
+
+/* Macro to define tables used to set the flags.
+ This is a list in braces of pairs in braces,
+ each pair being { "NAME", VALUE }
+ where VALUE is the bits to set or minus the bits to clear.
+ An empty string NAME is used to identify the default VALUE. */
+
+#define TARGET_SWITCHES \
+ { { "", TARGET_DEFAULT}}
+
+#define TARGET_DEFAULT 0
+
+\f
+/* target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+ in instructions that operate on numbered bit-fields. */
+#define BITS_BIG_ENDIAN 0
+
+/* Define this if most significant byte of a word is the lowest numbered. */
+/* That is true on the we32000. */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword is lowest numbered. */
+/* For we32000 we can decide arbitrarily
+ since there are no machine instructions for them. */
+#define WORDS_BIG_ENDIAN 1
+
+/* number of bits in an addressible storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+ Note that this is not necessarily the width of data type `int';
+ if using 16-bit ints on a we32000, this would still be 32.
+ But on a machine with 16-bit registers, this would be 16. */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes). */
+#define UNITS_PER_WORD 4
+
+/* Width in bits of a pointer.
+ See also the macro `Pmode' defined below. */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list. */
+#define PARM_BOUNDARY 32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned. */
+#define STACK_BOUNDARY 32
+
+/* Allocation boundary (in *bits*) for the code of a function. */
+#define FUNCTION_BOUNDARY 32
+
+/* Alignment of field after `int : 0' in a structure. */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* No data type wants to be aligned rounder than this. */
+#define BIGGEST_ALIGNMENT 32
+
+/* Every structure's size must be a multiple of this. */
+#define STRUCTURE_SIZE_BOUNDARY 32
+
+/* Define this if move instructions will actually fail to work
+ when given unaligned data. */
+#define STRICT_ALIGNMENT
+
+/* Define number of bits in most basic integer type.
+ (If undefined, default is BITS_PER_WORD). */
+#define INT_TYPE_SIZE 32
+
+/* Integer bit fields should have the same size and alignment
+ as actual integers */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+\f
+/* Standard register usage. */
+
+/* Number of actual hardware registers.
+ The hardware registers are assigned numbers for the compiler
+ from 0 to just below FIRST_PSEUDO_REGISTER.
+ All registers that the compiler knows about must be given numbers,
+ even those that are not normally considered general registers. */
+#define FIRST_PSEUDO_REGISTER 16
+
+/* 1 for registers that have pervasive standard uses
+ and are not available for the register allocator. */
+#define FIXED_REGISTERS \
+ {0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 1, 1, 1, 1, 1, 1, 1, }
+
+/* 1 for registers not available across function calls.
+ These must include the FIXED_REGISTERS and also any
+ registers that can be used without being saved.
+ The latter must include the registers where values are returned
+ and the register where structure-value addresses are passed.
+ Aside from that, you can include as many other registers as you like. */
+#define CALL_USED_REGISTERS \
+ {1, 1, 1, 0, 0, 0, 0, 0, \
+ 0, 1, 1, 1, 1, 1, 1, 1, }
+
+/* Make sure everything's fine if we *don't* have a given processor.
+ This assumes that putting a register in fixed_regs will keep the
+ compilers mitt's completely off it. We don't bother to zero it out
+ of register classes. */
+/* #define CONDITIONAL_REGISTER_USAGE */
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+ to hold something of mode MODE.
+ This is ordinarily the length in words of a value of mode MODE
+ but can be less for certain modes in special long registers. */
+#define HARD_REGNO_NREGS(REGNO, MODE) \
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
+#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+ when one has mode MODE1 and one has mode MODE2.
+ If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+ for any hard reg, then this must be 0 for correct output. */
+#define MODES_TIEABLE_P(MODE1, MODE2) 0
+
+/* Specify the registers used for certain standard purposes.
+ The values of these macros are register numbers. */
+
+/* Register used for the program counter */
+#define PC_REGNUM 15
+
+/* Register to use for pushing function arguments. */
+#define STACK_POINTER_REGNUM 12
+
+/* Base register for access to local variables of the function. */
+#define FRAME_POINTER_REGNUM 9
+
+/* Value should be nonzero if functions must have frame pointers.
+ Zero means the frame pointer need not be set up (and parms
+ may be accessed via the stack pointer) in functions that seem suitable.
+ This is computed in `reload', in reload1.c. */
+#define FRAME_POINTER_REQUIRED 1
+
+/* Base register for access to arguments of the function. */
+#define ARG_POINTER_REGNUM 10
+
+/* Register in which static-chain is passed to a function. */
+#define STATIC_CHAIN_REGNUM 8
+
+/* Register in which address to store a structure value
+ is passed to a function. */
+#define STRUCT_VALUE_REGNUM 2
+
+/* Order in which to allocate registers. */
+#define REG_ALLOC_ORDER \
+ {0, 1, 8, 7, 6, 5, 4, 3}
+\f
+/* Define the classes of registers for register constraints in the
+ machine description. Also define ranges of constants.
+
+ One of the classes must always be named ALL_REGS and include all hard regs.
+ If there is more than one class, another class must be named NO_REGS
+ and contain no registers.
+
+ The name GENERAL_REGS must be the name of a class (or an alias for
+ another name such as ALL_REGS). This is the class of registers
+ that is allowed by "g" or "r" in a register constraint.
+ Also, registers outside this class are allocated only when
+ instructions express preferences for them.
+
+ The classes must be numbered in nondecreasing order; that is,
+ a larger-numbered class must never be contained completely
+ in a smaller-numbered class.
+
+ For any two classes, it is very desirable that there be another
+ class that represents their union. */
+
+enum reg_class { NO_REGS, GENERAL_REGS,
+ ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file. */
+
+#define REG_CLASS_NAMES \
+ { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+ This is an initializer for a vector of HARD_REG_SET
+ of length N_REG_CLASSES. */
+
+#define REG_CLASS_CONTENTS \
+{ \
+ 0, /* NO_REGS */ \
+ 0x000017ff, /* GENERAL_REGS */ \
+ 0x0000ffff, /* ALL_REGS */ \
+}
+
+/* The same information, inverted:
+ Return the class number of the smallest class containing
+ reg number REGNO. This could be a conditional expression
+ or could index an array. */
+
+#define REGNO_REG_CLASS(REGNO) \
+ (((REGNO) < 11 || (REGNO) == 12) ? GENERAL_REGS : ALL_REGS)
+
+/* The class value for index registers, and the one for base regs. */
+
+#define INDEX_REG_CLASS NO_REGS
+#define BASE_REG_CLASS GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.
+ We do a trick here to modify the effective constraints on the
+ machine description; we zorch the constraint letters that aren't
+ appropriate for a specific target. This allows us to guarantee
+ that a specific kind of register will not be used for a given target
+ without fiddling with the register classes above. */
+
+#define REG_CLASS_FROM_LETTER(C) \
+ ((C) == 'r' ? GENERAL_REGS : NO_REGS)
+
+/* The letters I, J, K, L and M in a register constraint string
+ can be used to stand for particular ranges of immediate operands.
+ This macro defines what the ranges are.
+ C is the letter, and VALUE is a constant value.
+ Return 1 if VALUE is in the range specified by C. */
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C) 0
+
+/*
+ */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
+
+/* Given an rtx X being reloaded into a reg required to be
+ in class CLASS, return the class of reg to actually use.
+ In general this is just CLASS; but on some machines
+ in some cases it is preferable to use a more restrictive class. */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
+
+/* Return the maximum number of consecutive registers
+ needed to represent mode MODE in a register of class CLASS. */
+#define CLASS_MAX_NREGS(CLASS, MODE) \
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+\f
+/* Stack layout; function entry, exit and calling. */
+
+/* Define this if pushing a word on the stack
+ makes the stack pointer a smaller address. */
+/* #define STACK_GROWS_DOWNWARD */
+
+/* Define this if the nominal address of the stack frame
+ is at the high-address end of the local variables;
+ that is, each additional local variable allocated
+ goes at a more negative offset in the frame. */
+/* #define FRAME_GROWS_DOWNWARD */
+
+/* Offset within stack frame to start allocating local variables at.
+ If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+ first local allocated. Otherwise, it is the offset to the BEGINNING
+ of the first local allocated. */
+#define STARTING_FRAME_OFFSET 0
+
+/* If we generate an insn to push BYTES bytes,
+ this says how many the stack pointer really advances by. */
+#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
+
+/* Offset of first parameter from the argument pointer register value. */
+#define FIRST_PARM_OFFSET(FNDECL) 0
+
+/* Value is 1 if returning from a function call automatically
+ pops the arguments described by the number-of-args field in the call.
+ FUNTYPE is the data type of the function (as a tree),
+ or for a library call it is an identifier node for the subroutine name. */
+
+#define RETURN_POPS_ARGS(FUNTYPE,SIZE) (SIZE)
+
+/* Define how to find the value returned by a function.
+ VALTYPE is the data type of the value (as a tree).
+ If the precise function being called is known, FUNC is its FUNCTION_DECL;
+ otherwise, FUNC is 0. */
+
+/* On the we32000 the return value is in r0 regardless. */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+ gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
+
+/* Define how to find the value returned by a library function
+ assuming the value has mode MODE. */
+
+/* On the we32000 the return value is in r0 regardless. */
+
+#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
+
+/* 1 if N is a possible register number for a function value.
+ On the we32000, r0 is the only register thus used. */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
+
+/* Define this if PCC uses the nonreentrant convention for returning
+ structure and union values. */
+
+/* #define PCC_STATIC_STRUCT_RETURN */
+
+/* 1 if N is a possible register number for function argument passing.
+ On the we32000, no registers are used in this way. */
+
+#define FUNCTION_ARG_REGNO_P(N) 0
+\f
+/* Define a data type for recording info about an argument list
+ during the scan of that argument list. This data type should
+ hold all necessary information about the function itself
+ and about the args processed so far, enough to enable macros
+ such as FUNCTION_ARG to determine where the next arg should go.
+
+ On the we32k, this is a single integer, which is a number of bytes
+ of arguments scanned so far. */
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+ for a call to a function whose data type is FNTYPE.
+ For a library call, FNTYPE is 0.
+
+ On the we32k, the offset starts at 0. */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
+ ((CUM) = 0)
+
+/* Update the data in CUM to advance over an argument
+ of mode MODE and data type TYPE.
+ (TYPE is null for libcalls where that information may not be available.) */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
+ ((CUM) += ((MODE) != BLKmode \
+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
+ : (int_size_in_bytes (TYPE) + 3) & ~3))
+
+/* Define where to put the arguments to a function.
+ Value is zero to push the argument on the stack,
+ or a hard register in which to store the argument.
+
+ MODE is the argument's machine mode.
+ TYPE is the data type of the argument (as a tree).
+ This is null for libcalls where that information may
+ not be available.
+ CUM is a variable of type CUMULATIVE_ARGS which gives info about
+ the preceding args and about the function being called.
+ NAMED is nonzero if this argument is a named parameter
+ (otherwise it is an extra parameter matching an ellipsis). */
+
+/* On the we32000 all args are pushed */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
+
+/* For an arg passed partly in registers and partly in memory,
+ this is the number of registers used.
+ For args passed entirely in registers or entirely in memory, zero. */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
+
+/* This macro generates the assembly code for function entry.
+ FILE is a stdio stream to output the code to.
+ SIZE is an int: how many units of temporary storage to allocate.
+ Refer to the array `regs_ever_live' to determine which registers
+ to save; `regs_ever_live[I]' is nonzero if register number I
+ is ever used in the function. This macro is responsible for
+ knowing which registers should not be saved even if used. */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE) \
+{ register int nregs_to_save; \
+ register int regno; \
+ extern char call_used_regs[]; \
+ nregs_to_save = 0; \
+ for (regno = 8; regno > 2; regno--) \
+ if (regs_ever_live[regno] && ! call_used_regs[regno]) \
+ nregs_to_save = (9 - regno); \
+ fprintf (FILE, "\tsave &%d\n", nregs_to_save); \
+ if (SIZE) \
+ fprintf (FILE, "\taddw2 &%d,%%sp\n", ((SIZE) + 3) & ~3); }
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+ for profiling a function entry. */
+
+#define FUNCTION_PROFILER(FILE, LABELNO) \
+ fprintf (FILE, "\tmovw &.LP%d,%%r0\n\tjsb _mcount\n", (LABELNO))
+
+/* Output assembler code to FILE to initialize this source file's
+ basic block profiling info, if that has not already been done. */
+
+#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
+ fprintf (FILE, "\tcmpw .LPBX0,&0\n\tjne .LPI%d\n\tpushw &.LPBX0\n\tcall &1,__bb_init_func\n.LPI%d:\n", \
+ LABELNO, LABELNO);
+
+/* Output assembler code to FILE to increment the entry-count for
+ the BLOCKNO'th basic block in this source file. */
+
+#define BLOCK_PROFILER(FILE, BLOCKNO) \
+ fprintf (FILE, "\taddw2 &1,.LPBX2+%d\n", 4 * BLOCKNO)
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+ the stack pointer does not matter. The value is tested only in
+ functions that have frame pointers.
+ No definition is equivalent to always zero. */
+
+#define EXIT_IGNORE_STACK 0
+
+/* This macro generates the assembly code for function exit,
+ on machines that need it. If FUNCTION_EPILOGUE is not defined
+ then individual return instructions are generated for each
+ return statement. Args are same as for FUNCTION_PROLOGUE.
+
+ The function epilogue should not depend on the current stack pointer!
+ It should use the frame pointer only. This is mandatory because
+ of alloca; we also take advantage of it to omit stack adjustments
+ before returning. */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE) \
+{ register int nregs_to_restore; \
+ register int regno; \
+ extern char call_used_regs[]; \
+ nregs_to_restore = 0; \
+ for (regno = 8; regno > 2; regno--) \
+ if (regs_ever_live[regno] && ! call_used_regs[regno]) \
+ nregs_to_restore = (9 - regno); \
+ fprintf (FILE, "\tret &%d\n", nregs_to_restore); }
+
+/* Store in the variable DEPTH the initial difference between the
+ frame pointer reg contents and the stack pointer reg contents,
+ as of the start of the function body. This depends on the layout
+ of the fixed parts of the stack frame and on how registers are saved.
+
+ On the we32k, FRAME_POINTER_REQUIRED is always 1, so the definition of this
+ macro doesn't matter. But it must be defined. */
+
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0;
+
+/* Output assembler code for a block containing the constant parts
+ of a trampoline, leaving space for the variable parts. */
+
+/* On the we32k, the trampoline contains two instructions:
+ mov #STATIC,%r8
+ jmp #FUNCTION */
+
+#define TRAMPOLINE_TEMPLATE(FILE) \
+{ \
+ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x844f)); \
+ ASM_OUTPUT_SHORT (FILE, const0_rtx); \
+ ASM_OUTPUT_SHORT (FILE, const0_rtx); \
+ ASM_OUTPUT_CHAR (FILE, gen_rtx (CONST_INT, VOIDmode, 0x48)); \
+ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x247f)); \
+ ASM_OUTPUT_SHORT (FILE, const0_rtx); \
+ ASM_OUTPUT_SHORT (FILE, const0_rtx); \
+}
+
+/* Length in units of the trampoline for entering a nested function. */
+
+#define TRAMPOLINE_SIZE 13
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+ FNADDR is an RTX for the address of the function's pure code.
+ CXT is an RTX for the static chain value for the function. */
+
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+{ \
+ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
+ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 9)), FNADDR); \
+}
+\f
+/* Generate calls to memcpy() and memset() rather
+ than bcopy() and bzero() */
+#define TARGET_MEM_FUNCTIONS
+\f
+/* Addressing modes, and classification of registers for them. */
+
+/* #define HAVE_POST_INCREMENT */
+/* #define HAVE_POST_DECREMENT */
+
+/* #define HAVE_PRE_DECREMENT */
+/* #define HAVE_PRE_INCREMENT */
+
+/* Macros to check register numbers against specific register classes. */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+ They give nonzero only if REGNO is a hard reg of the suitable class
+ or a pseudo reg currently allocated to a suitable hard reg.
+ Since they use reg_renumber, they are safe only once reg_renumber
+ has been allocated, which happens in local-alloc.c. */
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) 0
+
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+ ((REGNO) < 11 || (REGNO) == 12 || \
+ (unsigned)reg_renumber[REGNO] < 11 || (unsigned)reg_renumber[REGNO] == 12)
+\f
+/* Maximum number of registers that can appear in a valid memory address. */
+
+#define MAX_REGS_PER_ADDRESS 1
+
+/* Recognize any constant value that is a valid address. */
+
+#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+ It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
+
+#define LEGITIMATE_CONSTANT_P(X) 1
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+ and check its validity for a certain class.
+ We have two alternate definitions for each of them.
+ The usual definition accepts all pseudo regs; the other rejects
+ them unless they have been allocated suitable hard regs.
+ The symbol REG_OK_STRICT causes the latter definition to be used.
+
+ Most source files want to accept pseudo regs in the hope that
+ they will get allocated to the class that the insn wants them to be in.
+ Source files for reload pass need to be strict.
+ After reload, it makes no difference, since pseudo regs have
+ been eliminated by then. */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+ or if it is a pseudo reg. */
+#define REG_OK_FOR_INDEX_P(X) 0
+
+/* Nonzero if X is a hard reg that can be used as a base reg
+ or if it is a pseudo reg. */
+#define REG_OK_FOR_BASE_P(X) \
+ (REGNO(X) < 11 || REGNO(X) == 12 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index. */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg. */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+\f
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+ that is a valid memory address for an instruction.
+ The MODE argument is the machine mode for the MEM expression
+ that wants to use this address. */
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
+{ register rtx Addr = X; \
+ if (REG_P(Addr) && REG_OK_FOR_BASE_P(Addr)) \
+ goto LABEL; \
+ if (CONSTANT_ADDRESS_P(Addr)) \
+ goto LABEL; \
+ if (GET_CODE(Addr) == PLUS && \
+ ((REG_P(XEXP(Addr, 0)) && REG_OK_FOR_BASE_P(XEXP(Addr, 0)) && \
+ CONSTANT_ADDRESS_P(XEXP(Addr, 1))) || \
+ (REG_P(XEXP(Addr, 1)) && REG_OK_FOR_BASE_P(XEXP(Addr, 1)) && \
+ CONSTANT_ADDRESS_P(XEXP(Addr, 0))))) \
+ goto LABEL; \
+}
+\f
+/* Try machine-dependent ways of modifying an illegitimate address
+ to be legitimate. If we find one, return the new, valid address.
+ This macro is used in only one place: `memory_address' in explow.c.
+
+ OLDX is the address as it was before break_out_memory_refs was called.
+ In some cases it is useful to look at this to decide what needs to be done.
+
+ MODE and WIN are passed so that this macro can use
+ GO_IF_LEGITIMATE_ADDRESS.
+
+ It is always safe for this macro to do nothing. It exists to recognize
+ opportunities to optimize the output. */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) { }
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+ has an effect that depends on the machine mode it is used for. */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) { }
+\f
+/* Specify the machine mode that this machine uses
+ for the index in the tablejump instruction. */
+#define CASE_VECTOR_MODE SImode
+
+/* Define this if the tablejump instruction expects the table
+ to contain offsets from the address of the table.
+ Do not define this if the table should contain absolute addresses. */
+/* #define CASE_VECTOR_PC_RELATIVE */
+
+/* Specify the tree operation to be used to convert reals to integers. */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case. */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0. */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* Max number of bytes we can move from memory to memory
+ in one reasonably fast instruction. */
+#define MOVE_MAX 4
+
+/* Define this if zero-extension is slow (more than one real instruction). */
+/* #define SLOW_ZERO_EXTEND */
+
+/* Nonzero if access to memory by bytes is slow and undesirable. */
+#define SLOW_BYTE_ACCESS 0
+
+/* Define if shifts truncate the shift count
+ which implies one can omit a sign-extension or zero-extension
+ of a shift count. */
+#define SHIFT_COUNT_TRUNCATED
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+ is done just by pretending it is already truncated. */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* We assume that the store-condition-codes instructions store 0 for false
+ and some other value for true. This is the value stored for true. */
+
+#define STORE_FLAG_VALUE -1
+
+/* When a prototype says `char' or `short', really pass an `int'. */
+#define PROMOTE_PROTOTYPES
+
+/* Specify the machine mode that pointers have.
+ After generation of rtl, the compiler makes no further distinction
+ between pointers and any other objects of this machine mode. */
+#define Pmode SImode
+
+/* A function address in a call instruction
+ is a byte address (for indexing purposes)
+ so give the MEM rtx a byte's mode. */
+#define FUNCTION_MODE QImode
+
+/* Compute the cost of computing a constant rtl expression RTX
+ whose rtx-code is CODE. The body of this macro is a portion
+ of a switch statement. If the code is computed here,
+ return it with a return statement. Otherwise, break from the switch. */
+
+#define CONST_COSTS(RTX,CODE) \
+ case CONST_INT: \
+ if ((unsigned) INTVAL (RTX) < 077) return 1; \
+ case CONST: \
+ case LABEL_REF: \
+ case SYMBOL_REF: \
+ return 3; \
+ case CONST_DOUBLE: \
+ return 5;
+\f
+/* Tell final.c how to eliminate redundant test instructions. */
+
+/* Here we define machine-dependent flags and fields in cc_status
+ (see `conditions.h'). */
+
+#define NOTICE_UPDATE_CC(EXP, INSN) \
+{ \
+ { CC_STATUS_INIT; } \
+}
+\f
+/* Control the assembler format that we output. */
+
+/* Use crt1.o as a startup file and crtn.o as a closing file. */
+
+#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
+
+#define ENDFILE_SPEC "crtn.o%s"
+
+/* The .file command should always begin the output. */
+
+#define ASM_FILE_START(FILE) output_file_directive ((FILE), main_input_filename)
+
+/* Output to assembler file text saying following lines
+ may contain character constants, extra white space, comments, etc. */
+
+#define ASM_APP_ON "#APP\n"
+
+/* Output to assembler file text saying following lines
+ no longer contain unusual constructs. */
+
+#define ASM_APP_OFF "#NO_APP\n"
+
+/* Output before code. */
+
+#define TEXT_SECTION_ASM_OP ".text"
+
+/* Output before writable data. */
+
+#define DATA_SECTION_ASM_OP ".data"
+
+/* Read-only data goes in the data section because
+ AT&T's assembler doesn't guarantee the proper alignment
+ of data in the text section even if an align statement
+ is used. */
+
+#define READONLY_DATA_SECTION() data_section()
+
+/* How to refer to registers in assembler output.
+ This sequence is indexed by compiler's hard-register-number (see above). */
+
+#define REGISTER_NAMES \
+{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+ "r8", "fp", "ap", "psw", "sp", "pcbp", "isp", "pc" }
+
+/* How to renumber registers for dbx and gdb. */
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+/* Output SDB debugging info in response to the -g option. */
+
+#define SDB_DEBUGGING_INFO
+
+/* This is how to output the definition of a user-level label named NAME,
+ such as the label on a static function or variable NAME. */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME) \
+ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+ defined for reference from other files. */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
+ do { \
+ fputs (".globl ", FILE); \
+ assemble_name (FILE, NAME); \
+ fputs ("\n", FILE); \
+ } while (0)
+
+/* This is how to output a reference to a user-level label named NAME.
+ `assemble_name' uses this. */
+
+#define ASM_OUTPUT_LABELREF(FILE,NAME) \
+ fprintf (FILE, "%s", NAME)
+
+/* This is how to output an internal numbered label where
+ PREFIX is the class of label and NUM is the number within the class. */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
+ fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
+
+/* This is how to store into the string LABEL
+ the symbol_ref name of an internal numbered label where
+ PREFIX is the class of label and NUM is the number within the class.
+ This is suitable for output with `assemble_name'. */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
+ sprintf (LABEL, ".%s%d", PREFIX, NUM)
+
+/* This is how to output an internal numbered label which
+ labels a jump table. */
+
+#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
+ do { \
+ ASM_OUTPUT_ALIGN (FILE, 2); \
+ ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
+ } while (0)
+
+/* Assembler pseudo to introduce byte constants. */
+
+#define ASM_BYTE_OP "\t.byte"
+
+/* This is how to output an assembler line defining a `double' constant. */
+
+/* This is how to output an assembler line defining a `float' constant. */
+
+/* AT&T's assembler can't handle floating constants written as floating.
+ However, when cross-compiling, always use that in case format differs. */
+
+#ifdef CROSS_COMPILER
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
+ fprintf (FILE, "\t.double 0r%.20g\n", (VALUE))
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
+ fprintf (FILE, "\t.float 0r%.10g\n", (VALUE))
+
+#else
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
+do { union { double d; long l[2];} tem; \
+ tem.d = (VALUE); \
+ fprintf (FILE, "\t.word 0x%x, 0x%x\n", tem.l[0], tem.l[1]);\
+ } while (0)
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
+do { union { float f; long l;} tem; \
+ tem.f = (VALUE); \
+ fprintf (FILE, "\t.word 0x%x\n", tem.l); \
+ } while (0)
+
+#endif /* not CROSS_COMPILER */
+
+/* This is how to output an assembler line defining an `int' constant. */
+
+#define ASM_OUTPUT_INT(FILE,VALUE) \
+( fprintf (FILE, "\t.word "), \
+ output_addr_const (FILE, (VALUE)), \
+ fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants. */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE) \
+( fprintf (FILE, "\t.half "), \
+ output_addr_const (FILE, (VALUE)), \
+ fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE) \
+( fprintf (FILE, "\t.byte "), \
+ output_addr_const (FILE, (VALUE)), \
+ fprintf (FILE, "\n"))
+
+/* This is how to output an assembler line for a numeric constant byte. */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE) \
+ fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+
+#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
+{ \
+ unsigned char *s; \
+ int i; \
+ for (i = 0, s = (PTR); i < (LEN); s++, i++) \
+ { \
+ if ((i % 8) == 0) \
+ fprintf ((FILE),"%s\t.byte\t",(i?"\n":"")); \
+ fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
+ } \
+ fputs ("\n", (FILE)); \
+}
+
+/* This is how to output an insn to push a register on the stack.
+ It need not be very fast code. */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
+ fprintf (FILE, "\tpushw %s\n", reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+ It need not be very fast code. */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
+ fprintf (FILE, "\tPOPW %s\n", reg_names[REGNO])
+
+/* This is how to output an element of a case-vector that is absolute. */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
+ fprintf (FILE, "\t.word .L%d\n", VALUE)
+
+/* This is how to output an element of a case-vector that is relative. */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
+ fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
+
+/* This is how to output an assembler line
+ that says to advance the location counter
+ to a multiple of 2**LOG bytes. */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG) \
+ if ((LOG) != 0) \
+ fprintf (FILE, "\t.align %d\n", 1 << (LOG))
+
+/* This is how to output an assembler line
+ that says to advance the location counter by SIZE bytes. */
+
+/* The `space' pseudo in the text segment outputs nop insns rather than 0s,
+ so we must output 0s explicitly in the text segment. */
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE) \
+ if (in_text_section ()) \
+ { \
+ int i; \
+ for (i = 0; i < (SIZE) - 20; i += 20) \
+ fprintf (FILE, "\t.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n"); \
+ if (i < (SIZE)) \
+ { \
+ fprintf (FILE, "\t.byte 0"); \
+ i++; \
+ for (; i < (SIZE); i++) \
+ fprintf (FILE, ",0"); \
+ fprintf (FILE, "\n"); \
+ } \
+ } \
+ else \
+ fprintf ((FILE), "\t.set .,.+%u\n", (SIZE))
+
+/* This says how to output an assembler line
+ to define a global common symbol. */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
+ do { \
+ data_section(); \
+ fputs ("\t.comm ", (FILE)); \
+ assemble_name ((FILE), (NAME)); \
+ fprintf ((FILE), ",%u\n", (SIZE)); \
+ } while (0)
+
+/* This says how to output an assembler line
+ to define a local common symbol. */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
+ do { \
+ data_section(); \
+ ASM_OUTPUT_ALIGN ((FILE), 2); \
+ ASM_OUTPUT_LABEL ((FILE), (NAME)); \
+ fprintf ((FILE), "\t.zero %u\n", (SIZE)); \
+ } while (0)
+
+/* Store in OUTPUT a string (made with alloca) containing
+ an assembler-name for a local static variable named NAME.
+ LABELNO is an integer which is different for each call. */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
+ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+/* Output #ident as a .ident. */
+
+#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME)
+
+/* Define the parentheses used to group arithmetic operations
+ in assembler code. */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences. */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+ CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+ For `%' followed by punctuation, CODE is the punctuation and X is null. */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0
+
+#define PRINT_OPERAND(FILE, X, CODE) \
+{ int i; \
+ if (GET_CODE (X) == REG) \
+ fprintf (FILE, "%%%s", reg_names[REGNO (X)]); \
+ else if (GET_CODE (X) == MEM) \
+ output_address (XEXP (X, 0)); \
+ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
+ { \
+ union { double d; long l[2]; } dtem; \
+ union { float f; long l; } ftem; \
+ \
+ dtem.l[0] = CONST_DOUBLE_LOW (X); \
+ dtem.l[1] = CONST_DOUBLE_HIGH (X); \
+ ftem.f = dtem.d; \
+ fprintf(FILE, "&0x%lx", ftem.l); \
+ } \
+ else { putc ('&', FILE); output_addr_const (FILE, X); }}
+\f
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
+{ register rtx Addr = ADDR; \
+ rtx offset; \
+ rtx reg; \
+ if (GET_CODE (Addr) == MEM) { \
+ putc ('*', FILE); \
+ Addr = XEXP (Addr, 0); \
+ if (GET_CODE (Addr) == REG) \
+ putc ('0', FILE); \
+ } \
+ switch (GET_CODE (Addr)) \
+ { \
+ case REG: \
+ fprintf (FILE, "(%%%s)", reg_names[REGNO (Addr)]); \
+ break; \
+ \
+ case PLUS: \
+ offset = NULL; \
+ if (CONSTANT_ADDRESS_P (XEXP (Addr, 0))) \
+ { \
+ offset = XEXP (Addr, 0); \
+ Addr = XEXP (Addr, 1); \
+ } \
+ else if (CONSTANT_ADDRESS_P (XEXP (Addr, 1))) \
+ { \
+ offset = XEXP (Addr, 1); \
+ Addr = XEXP (Addr, 0); \
+ } \
+ else \
+ abort(); \
+ if (REG_P (Addr)) \
+ reg = Addr; \
+ else \
+ abort(); \
+ output_addr_const(FILE, offset); \
+ fprintf(FILE, "(%%%s)", reg_names[REGNO(reg)]); \
+ break; \
+ \
+ default: \
+ if ( !CONSTANT_ADDRESS_P(Addr)) \
+ abort(); \
+ output_addr_const (FILE, Addr); \
+ }}
+\f
+/*
+Local variables:
+version-control: t
+End:
+*/
--- /dev/null
+;;- Machine description for GNU compiler
+;;- AT&T we32000 Version
+;; Contributed by John Wehle (john@feith1.uucp)
+;; Copyright (C) 1991-1992 Free Software Foundation, Inc.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 1, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+
+
+;;- instruction definitions
+
+;;- @@The original PO technology requires these to be ordered by speed,
+;;- @@ so that assigner will pick the fastest.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;;- When naming insn's (operand 0 of define_insn) be careful about using
+;;- names from other targets machine descriptions.
+\f
+;; move instructions
+
+(define_insn ""
+ [(set (match_operand:DF 0 "push_operand" "=m")
+ (match_operand:DF 1 "general_operand" "mrF"))]
+ ""
+ "*
+ {
+ output_push_double(&operands[1]);
+
+ return \"\";
+ }")
+
+(define_insn "movdf"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=mr")
+ (match_operand:DF 1 "general_operand" "mrF"))]
+ ""
+ "*
+ {
+ output_move_double(operands);
+
+ return \"\";
+ }")
+
+(define_insn ""
+ [(set (match_operand:SF 0 "push_operand" "=m")
+ (match_operand:SF 1 "general_operand" "mrF"))]
+ ""
+ "pushw %1")
+
+(define_insn "movsf"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
+ (match_operand:SF 1 "general_operand" "mrF"))]
+ ""
+ "movw %1, %0")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "push_operand" "=m")
+ (match_operand:DI 1 "general_operand" "mriF"))]
+ ""
+ "*
+ {
+ output_push_double(&operands[1]);
+
+ return \"\";
+ }")
+
+(define_insn "movdi"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=mr")
+ (match_operand:DI 1 "general_operand" "mriF"))]
+ ""
+ "*
+ {
+ output_move_double(operands);
+
+ return \"\";
+ }")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "push_operand" "=m")
+ (match_operand:SI 1 "general_operand" "mri"))]
+ ""
+ "pushw %1")
+
+(define_insn "movsi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (match_operand:SI 1 "general_operand" "mri"))]
+ ""
+ "movw %1, %0")
+
+(define_insn "movhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (match_operand:HI 1 "general_operand" "mri"))]
+ ""
+ "movh %1, %0")
+
+(define_insn "movqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (match_operand:QI 1 "general_operand" "mri"))]
+ ""
+ "movb %1, %0")
+\f
+;; add instructions
+
+(define_insn ""
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:DI 2 "general_operand" "oriF")))]
+ ""
+ "*
+ {
+ rtx label[1];
+ rtx lsw_operands[3];
+
+ if (GET_CODE (operands[0]) == REG)
+ lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+ else
+ if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
+ lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ else
+ abort();
+
+ if (GET_CODE (operands[2]) == REG)
+ lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+ else
+ if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
+ lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ else
+ if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ {
+ lsw_operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_HIGH(operands[2]));
+ operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_LOW(operands[2]));
+ }
+ else
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ lsw_operands[2] = operands[2];
+ operands[2] = const0_rtx;
+ }
+ else
+ abort();
+
+ label[0] = gen_label_rtx();
+ LABEL_NUSES(label[0]) = 1;
+
+ output_asm_insn(\"addw2 %2, %0\", operands);
+ output_asm_insn(\"addw2 %2, %0\", lsw_operands);
+ output_asm_insn(\"BCCB %l0\", label);
+ output_asm_insn(\"INCW %0\", operands);
+ output_asm_insn(\"%l0:\", label);
+
+ return \"\";
+ }")
+
+(define_insn "adddi3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
+ (plus:DI (match_operand:DI 1 "general_operand" "oriF")
+ (match_operand:DI 2 "general_operand" "oriF")))]
+ ""
+ "*
+ {
+ rtx label[1];
+ rtx lsw_operands[3];
+
+ if (GET_CODE (operands[0]) == REG)
+ lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+ else
+ if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
+ lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ else
+ abort();
+
+ if (GET_CODE (operands[1]) == REG)
+ lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
+ else
+ if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
+ lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
+ else
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ lsw_operands[1] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_HIGH(operands[1]));
+ operands[1] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_LOW(operands[1]));
+ }
+ else
+ if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ lsw_operands[1] = operands[1];
+ operands[1] = const0_rtx;
+ }
+ else
+ abort();
+
+ if (GET_CODE (operands[2]) == REG)
+ lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+ else
+ if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
+ lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ else
+ if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ {
+ lsw_operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_HIGH(operands[2]));
+ operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_LOW(operands[2]));
+ }
+ else
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ lsw_operands[2] = operands[2];
+ operands[2] = const0_rtx;
+ }
+ else
+ abort();
+
+ label[0] = gen_label_rtx();
+ LABEL_NUSES(label[0]) = 1;
+
+ output_asm_insn(\"addw3 %2, %1, %0\", operands);
+ output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands);
+ output_asm_insn(\"BCCB %l0\", label);
+ output_asm_insn(\"INCW %0\", operands);
+ output_asm_insn(\"%l0:\", label);
+
+ return \"\";
+ }")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "addw2 %2, %0")
+
+(define_insn "addsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (plus:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "addw3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "addh2 %2, %0")
+
+(define_insn "addhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (plus:HI (match_operand:HI 1 "general_operand" "mri")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "addh3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "addb2 %2, %0")
+
+(define_insn "addqi3"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (plus:QI (match_operand:QI 1 "general_operand" "mri")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "addb3 %2, %1, %0")
+\f
+;; subtract instructions
+
+(define_insn ""
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
+ (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:DI 2 "general_operand" "oriF")))]
+ ""
+ "*
+ {
+ rtx label[1];
+ rtx lsw_operands[3];
+
+ if (GET_CODE (operands[0]) == REG)
+ lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+ else
+ if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
+ lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ else
+ abort();
+
+ if (GET_CODE (operands[2]) == REG)
+ lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+ else
+ if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
+ lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ else
+ if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ {
+ lsw_operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_HIGH(operands[2]));
+ operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_LOW(operands[2]));
+ }
+ else
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ lsw_operands[2] = operands[2];
+ operands[2] = const0_rtx;
+ }
+ else
+ abort();
+
+ label[0] = gen_label_rtx();
+ LABEL_NUSES(label[0]) = 1;
+
+ output_asm_insn(\"subw2 %2, %0\", operands);
+ output_asm_insn(\"subw2 %2, %0\", lsw_operands);
+ output_asm_insn(\"BCCB %l0\", label);
+ output_asm_insn(\"DECW %0\", operands);
+ output_asm_insn(\"%l0:\", label);
+
+ return \"\";
+ }")
+
+(define_insn "subdi3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
+ (minus:DI (match_operand:DI 1 "general_operand" "oriF")
+ (match_operand:DI 2 "general_operand" "oriF")))]
+ ""
+ "*
+ {
+ rtx label[1];
+ rtx lsw_operands[3];
+
+ if (GET_CODE (operands[0]) == REG)
+ lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
+ else
+ if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
+ lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ else
+ abort();
+
+ if (GET_CODE (operands[1]) == REG)
+ lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
+ else
+ if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
+ lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
+ else
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ lsw_operands[1] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_HIGH(operands[1]));
+ operands[1] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_LOW(operands[1]));
+ }
+ else
+ if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ lsw_operands[1] = operands[1];
+ operands[1] = const0_rtx;
+ }
+ else
+ abort();
+
+ if (GET_CODE (operands[2]) == REG)
+ lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
+ else
+ if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
+ lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ else
+ if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ {
+ lsw_operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_HIGH(operands[2]));
+ operands[2] = gen_rtx(CONST_INT, SImode,
+ CONST_DOUBLE_LOW(operands[2]));
+ }
+ else
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ lsw_operands[2] = operands[2];
+ operands[2] = const0_rtx;
+ }
+ else
+ abort();
+
+ label[0] = gen_label_rtx();
+ LABEL_NUSES(label[0]) = 1;
+
+ output_asm_insn(\"subw3 %2, %1, %0\", operands);
+ output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands);
+ output_asm_insn(\"BCCB %l0\", label);
+ output_asm_insn(\"DECW %0\", operands);
+ output_asm_insn(\"%l0:\", label);
+
+ return \"\";
+ }")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "subw2 %2, %0")
+
+(define_insn "subsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (minus:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "subw3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "subh2 %2, %0")
+
+(define_insn "subhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (minus:HI (match_operand:HI 1 "general_operand" "mri")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "subh3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "subb2 %2, %0")
+
+(define_insn "subqi3"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (minus:QI (match_operand:QI 1 "general_operand" "mri")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "subb3 %2, %1, %0")
+\f
+;; signed multiply instructions
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "mulw2 %2, %0")
+
+(define_insn "mulsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (mult:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "mulw3 %2, %1, %0")
+
+;; signed divide instructions
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (div:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "divw2 %2, %0")
+
+(define_insn "divsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (div:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "divw3 %2, %1, %0")
+
+;; signed modulus instruction
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (mod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "modw2 %2, %0")
+
+(define_insn "modsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (mod:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "modw3 %2, %1, %0")
+\f
+;; unsigned divide instruction
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "udivw2 %2, %0")
+
+(define_insn "udivsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (udiv:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "udivw3 %2, %1, %0")
+
+;; unsigned modulus instruction
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (umod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "umodw2 %2, %0")
+
+(define_insn "umodsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (umod:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "umodw3 %2, %1, %0")
+\f
+;; logical-and instructions
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "andw2 %2, %0")
+
+(define_insn "andsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (and:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "andw3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "andh2 %2, %0")
+
+(define_insn "andhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (and:HI (match_operand:HI 1 "general_operand" "mri")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "andh3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "andb2 %2, %0")
+
+(define_insn "andqi3"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (and:QI (match_operand:QI 1 "general_operand" "mri")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "andb3 %2, %1, %0")
+\f
+;; inclusive-or instructions
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "orw2 %2, %0")
+
+(define_insn "iorsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (ior:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "orw3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "orh2 %2, %0")
+
+(define_insn "iorhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (ior:HI (match_operand:HI 1 "general_operand" "mri")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "orh3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "orb2 %2, %0")
+
+(define_insn "iorqi3"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (ior:QI (match_operand:QI 1 "general_operand" "mri")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "orb3 %2, %1, %0")
+\f
+;; exclusive-or instructions
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "xorw2 %2, %0")
+
+(define_insn "xorsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (xor:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "xorw3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "xorh2 %2, %0")
+
+(define_insn "xorhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (xor:HI (match_operand:HI 1 "general_operand" "mri")
+ (match_operand:HI 2 "general_operand" "mri")))]
+ ""
+ "xorh3 %2, %1, %0")
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "xorb2 %2, %0")
+
+(define_insn "xorqi3"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (xor:QI (match_operand:QI 1 "general_operand" "mri")
+ (match_operand:QI 2 "general_operand" "mri")))]
+ ""
+ "xorb3 %2, %1, %0")
+\f
+;; arithmetic shift instructions
+
+(define_insn "ashlsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (ashift:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "LLSW3 %2, %1, %0")
+
+(define_insn "ashrsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (ashiftrt:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "ARSW3 %2, %1, %0")
+
+;; logical shift instructions
+
+;; (define_insn "lshlsi3"
+;; [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+;; (lshift:SI (match_operand:SI 1 "general_operand" "mri")
+;; (match_operand:SI 2 "general_operand" "mri")))]
+;; ""
+;; "LLSW3 %2, %1, %0")
+
+(define_insn "lshrsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (lshiftrt:SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "LRSW3 %2, %1, %0")
+
+;; rotate instruction
+
+(define_insn "rotrsi3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (rotatert: SI (match_operand:SI 1 "general_operand" "mri")
+ (match_operand:SI 2 "general_operand" "mri")))]
+ ""
+ "ROTW %2, %1, %0")
+\f
+;; negate instructions
+
+(define_insn "negsi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (neg:SI (match_operand:SI 1 "general_operand" "mri")))]
+ ""
+ "mnegw %1, %0")
+
+(define_insn "neghi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (neg:HI (match_operand:HI 1 "general_operand" "mri")))]
+ ""
+ "mnegh %1, %0")
+
+;; complement instructions
+
+(define_insn "one_cmplsi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (not:SI (match_operand:SI 1 "general_operand" "mri")))]
+ ""
+ "mcomw %1, %0")
+
+(define_insn "one_cmplhi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (not:HI (match_operand:HI 1 "general_operand" "mri")))]
+ ""
+ "mcomh %1, %0")
+
+(define_insn "one_cmplqi2"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (not:QI (match_operand:QI 1 "general_operand" "mri")))]
+ ""
+ "mcomb %1, %0")
+\f
+;; compare instruction
+
+(define_insn "cmpsi"
+ [(set (cc0) (compare (match_operand:SI 0 "general_operand" "mri")
+ (match_operand:SI 1 "general_operand" "mri")))]
+ ""
+ "CMPW %1, %0")
+
+(define_insn "cmphi"
+ [(set (cc0) (compare (match_operand:HI 0 "general_operand" "mri")
+ (match_operand:HI 1 "general_operand" "mri")))]
+ ""
+ "*
+ {
+
+ if (GET_CODE (operands[0]) == CONST_INT &&
+ ((unsigned long)INTVAL (operands[0]) & 0x8000L))
+ operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffff0000L);
+
+ if (GET_CODE (operands[1]) == CONST_INT &&
+ ((unsigned long)INTVAL (operands[1]) & 0x8000L))
+ operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffff0000L);
+
+ output_asm_insn(\"CMPH %1, %0\",operands);
+
+ return \"\";
+ }")
+
+(define_insn "cmpqi"
+ [(set (cc0) (compare (match_operand:QI 0 "general_operand" "mri")
+ (match_operand:QI 1 "general_operand" "mri")))]
+ ""
+ "*
+ {
+
+ if (GET_CODE (operands[0]) == CONST_INT &&
+ ((unsigned long)INTVAL (operands[0]) & 0x80L))
+ operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffffff00L);
+
+ if (GET_CODE (operands[1]) == CONST_INT &&
+ ((unsigned long)INTVAL (operands[1]) & 0x80L))
+ operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffffff00L);
+
+ output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands);
+
+ return \"\";
+ }")
+
+;; test instruction
+
+(define_insn "tstsi"
+ [(set (cc0) (match_operand:SI 0 "general_operand" "mri"))]
+ ""
+ "TSTW %0")
+
+(define_insn "tsthi"
+ [(set (cc0) (match_operand:HI 0 "general_operand" "mri"))]
+ ""
+ "*
+ {
+
+ if (GET_CODE (operands[0]) == CONST_INT &&
+ ((unsigned long)INTVAL (operands[0]) & 0x8000L))
+ operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffff0000L);
+
+ output_asm_insn(\"TSTH %0\",operands);
+
+ return \"\";
+ }")
+
+(define_insn "tstqi"
+ [(set (cc0) (match_operand:QI 0 "general_operand" "mri"))]
+ ""
+ "*
+ {
+
+ if (GET_CODE (operands[0]) == CONST_INT &&
+ ((unsigned long)INTVAL (operands[0]) & 0x80L))
+ operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffffff00L);
+
+ output_asm_insn(\"TSTB {sbyte}%0\",operands);
+
+ return \"\";
+ }")
+\f
+;; truncate instructions
+
+(define_insn "truncdfsf2"
+ [(clobber (reg:SI 0))
+ (clobber (reg:SI 1))
+ (clobber (reg:SI 2))
+ (set (match_operand:SF 0 "nonimmediate_operand" "=mr")
+ (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))]
+ ""
+ "*
+ {
+ output_push_double(&operands[1]);
+ output_asm_insn(\"call &2, _fdtos\");
+
+ if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 0)
+ output_asm_insn(\"movw %%r0, %0\", operands);
+
+ return \"\";
+ }")
+
+
+(define_insn "truncsihi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (truncate:HI (match_operand:SI 1 "general_operand" "mri")))]
+ ""
+ "movtwh %1, %0")
+
+(define_insn "truncsiqi2"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (truncate:QI (match_operand:SI 1 "general_operand" "mri")))]
+ ""
+ "movtwb %1, %0")
+
+(define_insn "trunchiqi2"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
+ (truncate:QI (match_operand:HI 1 "general_operand" "mri")))]
+ ""
+ "movthb %1, %0")
+\f
+;; sign-extend move instructions
+
+(define_insn "extendsfdf2"
+ [(clobber (reg:SI 0))
+ (clobber (reg:SI 1))
+ (clobber (reg:SI 2))
+ (set (match_operand:DF 0 "nonimmediate_operand" "=or")
+ (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))]
+ ""
+ "*
+ {
+ rtx xoperands[2];
+
+ output_asm_insn(\"pushw %1\", operands);
+ output_asm_insn(\"call &1, _fstod\");
+
+ if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 0) {
+ xoperands[0] = operands[0];
+ xoperands[1] = gen_rtx(REG, DFmode, 0);
+ output_move_double(xoperands);
+ }
+
+ return \"\";
+ }")
+
+(define_insn "extendhisi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
+ ""
+ "movbhw %1, %0")
+
+(define_insn "extendqisi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
+ ""
+ "movbbw %1, %0")
+
+(define_insn "extendqihi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
+ ""
+ "movbbh %1, %0")
+
+;; zero-extend move instructions
+
+(define_insn "zero_extendhisi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
+ ""
+ "movzhw %1, %0")
+
+(define_insn "zero_extendqisi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+ (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
+ ""
+ "movzbw %1, %0")
+
+(define_insn "zero_extendqihi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
+ (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
+ ""
+ "movzbh %1, %0")
+\f
+;; bit field instructions
+
+;; (define_insn "extzv"
+;; [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
+;; (zero_extract:SI (match_operand:SI 1 "register_operand" "mr")
+;; (match_operand:SI 2 "general_operand" "mri")
+;; (match_operand:SI 3 "general_operand" "mri")))]
+;; ""
+;; "EXTFW %2, %3, %1, %0")
+
+;; (define_insn "insv"
+;; [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+mr")
+;; (match_operand:SI 1 "general_operand" "mri")
+;; (match_operand:SI 2 "general_operand" "mri"))
+;; (match_operand:SI 3 "general_operand" "mri"))]
+;; ""
+;; "INSFW %1, %2, %3, %0")
+\f
+;; conditional branch instructions
+
+(define_insn "beq"
+ [(set (pc) (if_then_else (eq (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "je %l0")
+
+(define_insn "bne"
+ [(set (pc) (if_then_else (ne (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jne %l0")
+
+(define_insn "bgt"
+ [(set (pc) (if_then_else (gt (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jg %l0")
+
+(define_insn "bgtu"
+ [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jgu %l0")
+
+(define_insn "blt"
+ [(set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jl %l0")
+
+(define_insn "bltu"
+ [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jlu %l0")
+
+(define_insn "bge"
+ [(set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jge %l0")
+
+(define_insn "bgeu"
+ [(set (pc) (if_then_else (geu (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jgeu %l0")
+
+(define_insn "ble"
+ [(set (pc) (if_then_else (le (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jle %l0")
+
+(define_insn "bleu"
+ [(set (pc) (if_then_else (leu (cc0) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "jleu %l0")
+\f
+;; reverse-conditional branch instructions
+
+(define_insn ""
+ [(set (pc) (if_then_else (eq (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jne %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (ne (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "je %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (gt (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jle %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jleu %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jge %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jgeu %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jl %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (geu (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jlu %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (le (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jg %l0")
+
+(define_insn ""
+ [(set (pc) (if_then_else (leu (cc0) (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "jgu %l0")
+\f
+;; call instructions
+
+(define_insn "call"
+ [(call (match_operand:QI 0 "memory_operand" "m")
+ (match_operand:SI 1 "immediate_operand" "i"))]
+ ""
+ "call %1/4, %0")
+
+(define_insn "call_value"
+ [(set (match_operand 0 "register_operand" "=r")
+ (call (match_operand:QI 1 "memory_operand" "m")
+ (match_operand:SI 2 "immediate_operand" "i")))]
+ ""
+ "call %2/4, %1")
+
+;; No-op instruction
+
+(define_insn "nop"
+ [(const_int 0)]
+ ""
+ "NOP")
+
+;; jump through a dispatch table instruction
+
+(define_expand "casesi"
+ [(use (match_operand:SI 0 "general_operand" "mri"))
+ (set (cc0) (compare (match_dup 5)
+ (match_operand:SI 1 "general_operand" "mri")))
+ (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (label_ref (match_operand 4 "" ""))
+ (pc)))
+ (set (match_dup 5) (minus:SI (match_dup 5)
+ (match_dup 1)))
+ (set (cc0) (compare (match_dup 5)
+ (match_operand:SI 2 "general_operand" "mri")))
+ (set (pc) (if_then_else (gtu (cc0) (const_int 0))
+ (label_ref (match_operand 4 "" ""))
+ (pc)))
+ (set (match_dup 5) (ashift:SI (match_dup 5)
+ (const_int 2)))
+ (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" ""))
+ (match_dup 5))))]
+ ""
+ "
+ {
+ operands[5] = gen_reg_rtx(GET_MODE (operands[0]));
+ emit_move_insn(operands[5], operands[0]);
+ }")
+
+;; jump instructions
+
+(define_insn ""
+ [(set (pc) (mem:SI (match_operand:SI 0 "address_operand" "p")))]
+ "GET_CODE (operands[0]) != MEM"
+ "jmp *%a0")
+
+(define_insn "indirect_jump"
+ [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
+ ""
+ "jmp %a0")
+
+(define_insn "jump"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ ""
+ "jmp %l0")
+\f
+;; peephole optimizations
+
+(define_peephole
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "nonimmediate_operand" "or"))
+ (set (match_operand:SI 2 "register_operand" "=r")
+ (mem:SI (match_dup 0)))]
+ "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))"
+ "movw %a1, %0")
+
+(define_peephole
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "nonimmediate_operand" "or"))
+ (set (match_operand:HI 2 "register_operand" "=r")
+ (mem:HI (match_dup 0)))]
+ "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))"
+ "movh %a1, %0")
+
+(define_peephole
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "nonimmediate_operand" "or"))
+ (set (match_operand:QI 2 "register_operand" "=r")
+ (mem:QI (match_dup 0)))]
+ "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))"
+ "movb %a1, %0")
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