NO_REGS, /* IIF/IOF No */
INT_REGS, /* RS QI No */
INT_REGS, /* RE QI No */
- INT_REGS, /* RC QI No */
+ RC_REG, /* RC QI No */
EXT_REGS, /* R8 QI, QF, HF QI */
EXT_REGS, /* R9 QI, QF, HF No */
EXT_REGS, /* R10 QI, QF, HF No */
}
+void
+c4x_optimization_options (level, size)
+ int level;
+ int size ATTRIBUTE_UNUSED;
+{
+ /* When optimizing, enable use of RPTB instruction. */
+ if (level >= 1)
+ flag_branch_on_count_reg = 1;
+}
/* Write an ASCII string. */
fprintf (stderr, ")\n");
}
if (reg)
- return gen_rtx (REG, mode, reg);
+ return gen_rtx_REG (mode, reg);
else
return NULL_RTX;
}
void
c4x_emit_libcall (name, code, dmode, smode, noperands, operands)
- const char *name;
+ char *name;
enum rtx_code code;
enum machine_mode dmode;
enum machine_mode smode;
rtx equiv;
start_sequence ();
- libcall = gen_rtx (SYMBOL_REF, Pmode, name);
+ libcall = gen_rtx_SYMBOL_REF (Pmode, name);
switch (noperands)
{
case 2:
void
c4x_emit_libcall_mulhi (name, code, mode, operands)
- const char *name;
+ char *name;
enum rtx_code code;
enum machine_mode mode;
rtx *operands;
rtx equiv;
start_sequence ();
- libcall = gen_rtx (SYMBOL_REF, Pmode, name);
+ libcall = gen_rtx_SYMBOL_REF (Pmode, name);
ret = emit_library_call_value (libcall, NULL_RTX, 1, mode, 2,
operands[1], mode, operands[2], mode);
- equiv = gen_rtx (TRUNCATE, mode,
- gen_rtx (LSHIFTRT, HImode,
- gen_rtx (MULT, HImode,
+ equiv = gen_rtx_TRUNCATE (mode,
+ gen_rtx_LSHIFTRT (HImode,
+ gen_rtx_MULT (HImode,
gen_rtx (code, HImode, operands[1]),
gen_rtx (code, HImode, operands[2])),
- gen_rtx (CONST_INT, VOIDmode, 32)));
+ gen_rtx_CONST_INT (VOIDmode, 32)));
insns = get_insns ();
end_sequence ();
emit_libcall_block (insns, operands[0], ret, equiv);
enum reg_class
c4x_limit_reload_class (mode, class)
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
enum reg_class class;
{
return class;
enum reg_class
c4x_secondary_memory_needed (class1, class2, mode)
- enum reg_class class1;
- enum reg_class class2;
- enum machine_mode mode;
+ enum reg_class class1 ATTRIBUTE_UNUSED;
+ enum reg_class class2 ATTRIBUTE_UNUSED;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return 0;
}
rtx
c4x_legitimize_address (orig, mode)
- rtx orig;
- enum machine_mode mode;
+ rtx orig ATTRIBUTE_UNUSED;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return NULL_RTX;
}
&& (code == LE || code == GE || code == LT || code == GT))
return NULL_RTX;
- cc_reg = gen_rtx (REG, mode, ST_REGNO);
- emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
- gen_rtx (COMPARE, mode, x, y)));
+ cc_reg = gen_rtx_REG (mode, ST_REGNO);
+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
+ gen_rtx_COMPARE (mode, x, y)));
return cc_reg;
}
addr = XEXP (addr, 0);
if (GET_CODE (addr) == CONST_INT)
{
- op1 = gen_rtx (CONST_INT, VOIDmode, INTVAL (addr) & ~0xffff);
+ op1 = gen_rtx_CONST_INT (VOIDmode, INTVAL (addr) & ~0xffff);
emit_insn_before (gen_movqi (operand0, op1), insn);
- op1 = gen_rtx (CONST_INT, VOIDmode, INTVAL (addr) & 0xffff);
+ op1 = gen_rtx_CONST_INT (VOIDmode, INTVAL (addr) & 0xffff);
emit_insn_before (gen_iorqi3_noclobber (operand0,
operand0, op1), insn);
delete_insn (insn);
}
}
if (!TARGET_SMALL)
- emit_insn_before (gen_set_ldp (gen_rtx (REG, Pmode, DP_REGNO),
+ emit_insn_before (gen_set_ldp (gen_rtx_REG (Pmode, DP_REGNO),
operand), insn);
/* Replace old memory reference with direct reference. */
- *newop = gen_rtx (MEM, GET_MODE (operand),
- gen_rtx (PLUS, Pmode,
- gen_rtx (REG, Pmode, DP_REGNO), op0));
+ *newop = gen_rtx_MEM (GET_MODE (operand),
+ gen_rtx_PLUS (Pmode,
+ gen_rtx_REG (Pmode, DP_REGNO),
+ op0));
/* Use change_address? */
MEM_VOLATILE_P (*newop) = MEM_VOLATILE_P (operand);
break;
op0 = XEXP (force_const_mem (Pmode, operand), 0);
- *newop = gen_rtx (MEM, GET_MODE (operand),
- gen_rtx (PLUS, Pmode,
- gen_rtx (PLUS, Pmode,
- gen_rtx (USE, VOIDmode, operand),
- gen_rtx (REG, Pmode, DP_REGNO)),
- op0));
-
+ *newop = gen_rtx_MEM (GET_MODE (operand),
+ gen_rtx_PLUS (Pmode,
+ gen_rtx_PLUS (Pmode,
+ gen_rtx_USE (VOIDmode, operand),
+ gen_rtx_REG (Pmode, DP_REGNO)),
+ op0));
+
if (!TARGET_SMALL)
- emit_insn_before (gen_set_ldp_use (gen_rtx (REG, Pmode, DP_REGNO),
+ emit_insn_before (gen_set_ldp_use (gen_rtx_REG (Pmode, DP_REGNO),
*newop, operand), insn);
return 0;
Note that we cannot have a call insn, since we don't generate
repeat loops with calls in them (although I suppose we could, but
- there's no benefit.) */
+ there's no benefit.)
+
+ !!! FIXME. The rptb_top insn may be sucked into a SEQUENCE. */
int
c4x_rptb_nop_p (insn)
rtx insn;
{
+ rtx start_label;
int i;
+ /* Extract the start label from the jump pattern (rptb_end). */
+ start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
+
/* If there is a label at the end of the loop we must insert
a NOP. */
insn = prev_nonnote_insn (insn);
/* Search back for prev non-note and non-label insn. */
while (GET_CODE (insn) == NOTE || GET_CODE (insn) == CODE_LABEL
|| GET_CODE (insn) == USE || GET_CODE (insn) == CLOBBER)
- insn = PREV_INSN (insn);
+ {
+ if (insn == start_label)
+ return i == 0;
+
+ insn = PREV_INSN (insn);
+ };
- /* I we have a jump instruction we should insert a NOP. If we
+ /* If we have a jump instruction we should insert a NOP. If we
hit repeat block top we should only insert a NOP if the loop
is empty. */
if (GET_CODE (insn) == JUMP_INSN)
return 1;
- else if (recog_memoized (insn) == CODE_FOR_rptb_top)
- return i == 0;
insn = PREV_INSN (insn);
}
return 0;
}
+void
+c4x_rptb_insert (insn)
+ rtx insn;
+{
+ rtx end_label;
+ rtx start_label;
+
+ /* Extract the start label from the jump pattern (rptb_end). */
+ start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
+
+ /* We'll have to update the basic blocks. */
+ end_label = gen_label_rtx ();
+ emit_label_after (end_label, insn);
+
+ for (; insn; insn = PREV_INSN (insn))
+ if (insn == start_label)
+ break;
+ if (!insn)
+ fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label);
+
+ /* We'll have to update the basic blocks. */
+ emit_insn_before (gen_rptb_top (start_label, end_label), insn);
+}
+
/* This function is a C4x special. It scans through all the insn
operands looking for places where the DP register needs to be
reloaded and for large immediate operands that need to be converted
c4x_process_after_reload (first)
rtx first;
{
- rtx operand0;
rtx insn;
int i;
/* Look for insn. */
if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
{
- int noperands;
int insn_code_number;
insn_code_number = recog_memoized (insn);
if (insn_code_number < 0)
continue;
+ /* Insert the RTX for RPTB at the top of the loop
+ and a label at the end of the loop. */
+ if (insn_code_number == CODE_FOR_rptb_end)
+ c4x_rptb_insert(insn);
+
/* We split all insns here if they have a # for the output
template if we are using the big memory model since there
is a chance that we might be accessing memory across a
/* Do we have to update the basic block info here?
Maybe reorg wants it sorted out... */
- /* Continue with the first of the new insns gnerated
+ /* Continue with the first of the new insns generated
by the split. */
insn = new;
}
/* Ignore jumps and calls. */
- if (GET_CODE (insn) == CALL_INSN
- || GET_CODE (insn) == JUMP_INSN)
- {
- continue; /* Hopefully we are not hosed here. */
- }
-
- noperands = insn_n_operands[insn_code_number];
+ if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
+ continue;
insn_extract (insn);
-
- operand0 = recog_operand[0];
-
- for (i = 0; i < noperands; i++)
- if (c4x_scan_for_ldp (recog_operand_loc[i], insn, operand0))
+ for (i = 0; i < insn_n_operands[insn_code_number]; i++)
+ if (c4x_scan_for_ldp (recog_operand_loc[i], insn,
+ recog_operand[0]))
break;
}
}
int
c4x_autoinc_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) == MEM)
{
int
any_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+ register rtx op ATTRIBUTE_UNUSED;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return 1;
}
int
stik_const_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return c4x_K_constant (op);
}
int
not_const_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return c4x_N_constant (op);
}
int
reg_imm_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (REG_P (op) || CONSTANT_P (op))
return 1;
int
not_modify_reg (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (REG_P (op) || CONSTANT_P (op))
return 1;
int
not_rc_reg (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (REG_P (op) && REGNO (op) == RC_REGNO)
return 0;
int
dp_reg_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_DP_OR_PSEUDO_REGNO (op);
}
int
sp_reg_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_SP_OR_PSEUDO_REGNO (op);
}
int
st_reg_operand (op, mode)
register rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return REG_P (op) && IS_ST_OR_PSEUDO_REGNO (op);
}
+/* RC register. */
+
+int
+rc_reg_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ return REG_P (op) && IS_RC_OR_PSEUDO_REGNO (op);
+}
+
+
int
call_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) != MEM)
return 0;
int
valid_parallel_operands_4 (operands, mode)
rtx *operands;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
rtx op0 = operands[0];
rtx op1 = operands[1];
int
valid_parallel_operands_5 (operands, mode)
rtx *operands;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
int regs = 0;
rtx op0 = operands[1];
int
valid_parallel_operands_6 (operands, mode)
rtx *operands;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
int regs = 0;
rtx op0 = operands[1];
a positive count, so we emit a NEG. */
if ((code == ASHIFTRT || code == LSHIFTRT)
&& (GET_CODE (operands[2]) != CONST_INT))
- operands[2] = gen_rtx (NEG, mode, negate_rtx (mode, operands[2]));
+ operands[2] = gen_rtx_NEG (mode, negate_rtx (mode, operands[2]));
return 1;
}
mode = QImode;
else if (mode == HFmode)
mode = QFmode;
- return gen_rtx (MEM, mode, XEXP (op, 0));
+ return gen_rtx_MEM (mode, XEXP (op, 0));
case POST_DEC:
case PRE_DEC:
int
c4x_handle_pragma (p_getc, p_ungetc, pname)
int (* p_getc) PROTO ((void));
- void (* p_ungetc) PROTO ((int));
+ void (* p_ungetc) PROTO ((int)) ATTRIBUTE_UNUSED;
char *pname;
{
int i;
}
name[i] = 0;
sect = build_string (i, name);
- TREE_TYPE (sect) = char_array_type_node;
free (name);
sect = build_tree_list (NULL_TREE, sect);
int
c4x_valid_type_attribute_p (type, attributes, identifier, args)
tree type;
- tree attributes;
+ tree attributes ATTRIBUTE_UNUSED;
tree identifier;
- tree args;
+ tree args ATTRIBUTE_UNUSED;
{
if (TREE_CODE (type) != FUNCTION_TYPE)
return 0;
return 0;
}
- pack = gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, set1, set2));
+ pack = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2));
num_clobbers = 0;
if ((insn_code_number = recog (pack, pack, &num_clobbers)) < 0)
return 0;
rtx newpack;
int i;
- newpack = gen_rtx (PARALLEL, VOIDmode,
- gen_rtvec (GET_CODE (pack) == PARALLEL
+ newpack = gen_rtx_PARALLEL (VOIDmode,
+ gen_rtvec (GET_CODE (pack) == PARALLEL
? XVECLEN (pack, 0) + num_clobbers
: num_clobbers + 1));
/* Copy the REG_NOTES from insn to the new insn. */
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
- REG_NOTES (new) = gen_rtx (GET_CODE (note),
- REG_NOTE_KIND (note),
- XEXP (note, 0),
- REG_NOTES (new));
+ REG_NOTES (new) = gen_rtx (GET_CODE (note),
+ REG_NOTE_KIND (note),
+ XEXP (note, 0),
+ REG_NOTES (new));
/* Handle all the registers within insn and update the reg info. */
c4x_update_info_regs (PATTERN (insn), bb);
remove_note (insn, note);
}
for (note = REG_NOTES (insn2); note; note = XEXP (note, 1))
- REG_NOTES (insn) = gen_rtx (GET_CODE (note),
+ REG_NOTES (insn) = gen_rtx (GET_CODE (note),
REG_NOTE_KIND (note),
XEXP (note, 0),
REG_NOTES (insn));
{
/* The loop count must be more than 1 surely? */
SET_SRC (loop_count_set)
- = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (SET_SRC (loop_count_set)) -1);
+ = gen_rtx_CONST_INT (VOIDmode,
+ INTVAL (SET_SRC (loop_count_set)) -1);
}
else if (GET_CODE (SET_SRC (loop_count_set)) == PLUS
&& GET_CODE (XEXP (SET_SRC (loop_count_set), 1))
== CONST_INT)
{
XEXP (SET_SRC (loop_count_set), 1)
- = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (XEXP (SET_SRC (loop_count_set), 1))
- - 1);
+ = gen_rtx_CONST_INT (VOIDmode,
+ INTVAL (XEXP (SET_SRC (loop_count_set), 1))
+ - 1);
}
else
{
start_sequence ();
expand_binop (QImode, sub_optab,
- gen_rtx (REG, QImode, RC_REGNO),
- gen_rtx (CONST_INT, VOIDmode, 1),
- gen_rtx (REG, QImode, RC_REGNO),
+ gen_rtx_REG (QImode, RC_REGNO),
+ gen_rtx_CONST_INT (VOIDmode, 1),
+ gen_rtx_REG (QImode, RC_REGNO),
1, OPTAB_DIRECT);
seq_start = get_insns ();
end_sequence ();
/* Check this. What if we emit more than one insn?
Can we emit more than one insn? */
REG_NOTES (seq_start)
- = gen_rtx (EXPR_LIST, REG_UNUSED,
- gen_rtx (REG, QImode, RC_REGNO),
+ = gen_rtx_EXPR_LIST (REG_UNUSED,
+ gen_rtx_REG (QImode, RC_REGNO),
REG_NOTES (seq_start));
}
start_sequence ();
- emit_cmp_insn (gen_rtx (REG, QImode, RC_REGNO),
+ emit_cmp_insn (gen_rtx_REG (QImode, RC_REGNO),
const0_rtx, LT, NULL_RTX, QImode, 0, 0);
emit_jump_insn (gen_blt (end_label));
seq_start = get_insns ();
/* This is a bit of a hack... */
REG_NOTES (NEXT_INSN (seq_start))
- = gen_rtx (EXPR_LIST, REG_DEAD,
- gen_rtx (REG, QImode, RC_REGNO),
+ = gen_rtx_EXPR_LIST (REG_DEAD,
+ gen_rtx_REG (QImode, RC_REGNO),
REG_NOTES (NEXT_INSN (seq_start)));
if (TARGET_DEVEL)
static void
c4x_combine_parallel_independent (insns)
- rtx insns;
+ rtx insns ATTRIBUTE_UNUSED;
{
/* Combine independent insns like
(set (mem (reg 0)) (reg 1))
}
loop_info->off_by_one = (cc == LT || cc == LTU || cc == GT || cc == GTU);
- loop_info->unsigned_p |= (cc == LTU || cc == LEU || cc == GTU || cc == GEU);
+
/* We have a switch to allow an unsigned loop counter.
We'll normally disallow this case since the the repeat
/* If have a known constant loop count, things are easy... */
if (loop_info->loop_count > 0)
- return gen_rtx (CONST_INT, VOIDmode, loop_info->loop_count - 1);
+ return gen_rtx_CONST_INT (VOIDmode, loop_info->loop_count - 1);
if (loop_info->shift < 0)
abort ();
/* (end_value - start_value + adjust) >> shift */
result = expand_binop (QImode, loop_info->unsigned_p ?
lshr_optab : ashr_optab, result,
- gen_rtx (CONST_INT, VOIDmode,
+ gen_rtx_CONST_INT (VOIDmode,
loop_info->shift),
0, loop_info->unsigned_p, OPTAB_DIRECT);
}
/* ((end_value - start_value + adjust) >> shift) - 1 */
result = expand_binop (QImode, sub_optab,
- result, gen_rtx (CONST_INT, VOIDmode, 1),
+ result, gen_rtx_CONST_INT (VOIDmode, 1),
0, loop_info->unsigned_p, OPTAB_DIRECT);
seq_start = get_insns ();
bypass_label = NEXT_INSN (loop_end);
#if 0
- forced_labels = gen_rtx (EXPR_LIST, VOIDmode,
+ forced_labels = gen_rtx_EXPR_LIST (VOIDmode,
end_label, forced_labels);
- forced_labels = gen_rtx (EXPR_LIST, VOIDmode,
+ forced_labels = gen_rtx_EXPR_LIST (VOIDmode,
bypass_label, forced_labels);
#endif
emit_insn_after (gen_repeat_block_filler (), end_label);
}
+/* !!! FIXME to emit RPTS correctly. */
int
c4x_rptb_rpts_p (insn, op)
rtx insn, op;
extern void c4x_override_options ();
#define OVERRIDE_OPTIONS c4x_override_options ()
+/* Define this to change the optimizations performed by default. */
+extern void c4x_optimization_options ();
+#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL,SIZE)
/* Run Time Target Specification */
/* Misc registers */
#define IS_ST_REG(r) ((r) == ST_REGNO)
+#define IS_RC_REG(r) ((r) == RC_REGNO)
#define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
/* Composite register sets */
#define IS_DP_OR_PSEUDO_REG(r) (IS_DP_REG(r) || IS_PSEUDO_REG(r))
#define IS_SP_OR_PSEUDO_REG(r) (IS_SP_REG(r) || IS_PSEUDO_REG(r))
#define IS_ST_OR_PSEUDO_REG(r) (IS_ST_REG(r) || IS_PSEUDO_REG(r))
+#define IS_RC_OR_PSEUDO_REG(r) (IS_RC_REG(r) || IS_PSEUDO_REG(r))
#define IS_PSEUDO_REGNO(op) (IS_PSEUDO_REG(REGNO(op)))
#define IS_ADDR_REGNO(op) (IS_ADDR_REG(REGNO(op)))
#define IS_DP_OR_PSEUDO_REGNO(op) (IS_DP_OR_PSEUDO_REG(REGNO(op)))
#define IS_SP_OR_PSEUDO_REGNO(op) (IS_SP_OR_PSEUDO_REG(REGNO(op)))
#define IS_ST_OR_PSEUDO_REGNO(op) (IS_ST_OR_PSEUDO_REG(REGNO(op)))
+#define IS_RC_OR_PSEUDO_REGNO(op) (IS_RC_OR_PSEUDO_REG(REGNO(op)))
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
EXT_REGS, /* 'f' */
ADDR_REGS, /* 'a' */
INDEX_REGS, /* 'x' */
- SP_REG, /* 'b' */
BK_REG, /* 'k' */
+ SP_REG, /* 'b' */
+ RC_REG, /* 'v' */
INT_REGS, /* 'c' */
GENERAL_REGS, /* 'r' */
DP_REG, /* 'z' */
"EXT_REGS", \
"ADDR_REGS", \
"INDEX_REGS", \
- "SP_REG", \
"BK_REG", \
+ "SP_REG", \
+ "RC_REG", \
"INT_REGS", \
"GENERAL_REGS", \
"DP_REG", \
"ST_REG", \
"ALL_REGS" \
-};
+}
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
0xf00000ff, /* 'f' R0-R11 */ \
0x0000ff00, /* 'a' AR0-AR7 */ \
0x00060000, /* 'x' IR0-IR1 */ \
- 0x00100000, /* 'b' SP */ \
0x00080000, /* 'k' BK */ \
+ 0x00100000, /* 'b' SP */ \
+ 0x08000000, /* 'v' RC */ \
0x0e1eff00, /* 'c' AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */ \
0xfe1effff, /* 'r' R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */\
0x00010000, /* 'z' DP */ \
q - r0-r7
t - r0-r1
u - r2-r3
+ v - repeat count (rc)
x - index register (ir0-ir1)
y - status register (st)
z - dp reg (dp)
: ((CC) == 'q') ? EXT_LOW_REGS \
: ((CC) == 't') ? R0R1_REGS \
: ((CC) == 'u') ? R2R3_REGS \
+ : ((CC) == 'v') ? RC_REG \
: ((CC) == 'x') ? INDEX_REGS \
: ((CC) == 'y') ? ST_REG \
: ((CC) == 'z') ? DP_REG \
LABEL_REF, SYMBOL_REF, CONST, and HIGH codes. */
#define LEGITIMATE_CONSTANT_P(X) \
- (GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X) \
- || GET_CODE (X) == CONST_INT && c4x_I_constant (X))
+ ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
+ || (GET_CODE (X) == CONST_INT && c4x_I_constant (X)))
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
} while (0)
/* The TI tooling uses atexit. */
-#define ON_EXIT(FUNC,ARG) atexit (FUNC)
+#define HAVE_ATEXIT
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
{"dp_reg_operand", {REG}}, \
{"sp_reg_operand", {REG}}, \
{"st_reg_operand", {REG}}, \
+ {"rc_reg_operand", {REG}}, \
{"call_operand", {REG, SYMBOL_REF}}, \
{"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
{"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
extern int not_const_operand ();
+extern int parallel_operand ();
+
+extern int reg_or_const_operand ();
+
extern int reg_operand ();
extern int reg_imm_operand ();
extern int src_operand ();
+extern int src_hi_operand ();
+
extern int lsrc_operand ();
extern int tsrc_operand ();
if (!TARGET_C3X && which_alternative == 3)
{
- operands[1] = gen_rtx (CONST_INT, VOIDmode,
- (INTVAL (operands[1]) >> 16) & 0xffff);
+ operands[1] = gen_rtx_CONST_INT (VOIDmode,
+ (INTVAL (operands[1]) >> 16) & 0xffff);
return \"ldhi\\t%1,%0\";
}
"*
if (INTVAL (operands[2]) == 8)
{
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lb%3\\t%1,%0\";
}
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lh%3\\t%1,%0\";
"
[(set_attr "type" "binarycc,binary")
"*
if (INTVAL (operands[2]) == 8)
{
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lb%3\\t%1,%0\";
}
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lh%3\\t%1,%0\";
"
[(set_attr "type" "binarycc")
"*
if (INTVAL (operands[2]) == 8)
{
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lb%3\\t%1,%0\";
}
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lh%3\\t%1,%0\";
"
[(set_attr "type" "binarycc")
"*
if (INTVAL (operands[2]) == 8)
{
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lbu%3\\t%1,%0\";
}
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lhu%3\\t%1,%0\";
"
[(set_attr "type" "binarycc,binary")
"*
if (INTVAL (operands[2]) == 8)
{
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lbu%3\\t%1,%0\";
}
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lhu%3\\t%1,%0\";
"
[(set_attr "type" "binarycc")
"*
if (INTVAL (operands[2]) == 8)
{
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lbu%3\\t%1,%0\";
}
- operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16);
+ operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lhu%3\\t%1,%0\";
"
[(set_attr "type" "binarycc")
"*
if (INTVAL (operands[1]) == 8)
{
- operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 8);
+ operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 8);
return \"mb%2\\t%3,%0\";
}
else if (INTVAL (operands[1]) == 16)
{
- operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 16);
+ operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 16);
return \"mh%2\\t%3,%0\";
}
return \"lwl1\\t%3,%0\";
"*
if (INTVAL (operands[1]) == 8)
{
- operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 8);
+ operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 8);
return \"mb%2\\t%3,%0\";
}
- operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 16);
+ operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 16);
return \"mh%2\\t%3,%0\";
"
[(set_attr "type" "binarycc")
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
if (ccreg == NULL_RTX) FAIL;
- emit_insn (gen_rtx (SET, QImode, operands[0],
- gen_rtx (IF_THEN_ELSE, QImode,
+ emit_insn (gen_rtx_SET (QImode, operands[0],
+ gen_rtx_IF_THEN_ELSE (QImode,
gen_rtx (code, VOIDmode, ccreg, const0_rtx),
operands[2], operands[3])));
DONE;}")
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
if (ccreg == NULL_RTX) FAIL;
- emit_insn (gen_rtx (SET, QFmode, operands[0],
- gen_rtx (IF_THEN_ELSE, QFmode,
+ emit_insn (gen_rtx_SET (QFmode, operands[0],
+ gen_rtx_IF_THEN_ELSE (QFmode,
gen_rtx (code, VOIDmode, ccreg, const0_rtx),
operands[2], operands[3])));
DONE;}")
else
return \"call\\t%C0\";
}
- if (which_alternative == 1)
+ else
{
if (final_sequence)
return \"laju\\t%R0\";
else
return \"call\\t%C1\";
}
- if (which_alternative == 1)
+ else
{
if (final_sequence)
return \"laju\\t%R1\";
; operand 0 is the loop depth
; operand 1 is the loop count
+; operand 2 is the start label
+; operand 3 is the end label
(define_expand "repeat_block_top"
[(set (reg:QI 27) (match_operand:QI 1 "src_operand" ""))
(use (match_operand:QI 0 "immediate_operand" ""))
[(set_attr "type" "repeat")])
+(define_insn "rptb_end"
+ [(set (pc)
+ (if_then_else (ne (match_operand:QI 0 "rc_reg_operand" "v")
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))
+ (use (reg:QI 25))
+ (use (reg:QI 26))
+ (set (match_dup 0)
+ (plus:QI (match_dup 0)
+ (const_int -1)))]
+ ""
+ "*
+ return c4x_rptb_nop_p(insn) ? \"nop\" : \"\";"
+ [(set_attr "type" "repeat")])
+
+
+(define_expand "decrement_and_branch_on_count"
+ [(parallel [(set (pc)
+ (if_then_else (ne (match_operand:QI 0 "rc_reg_operand" "v")
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))
+ (use (reg:QI 25))
+ (use (reg:QI 26))
+ (set (match_dup 0) (plus:QI (match_dup 0) (const_int -1)))])]
+ ""
+ "")
+
+
(define_expand "movstrqi_small2"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
(mem:BLK (match_operand:BLK 1 "src_operand" "")))
len = INTVAL (operands[2]);
tmp = operands[4];
- src_mem = gen_rtx (MEM, QImode, src);
- dst_mem = gen_rtx (MEM, QImode, dst);
+ src_mem = gen_rtx_MEM (QImode, src);
+ dst_mem = gen_rtx_MEM (QImode, dst);
emit_insn (gen_movqi (tmp, src_mem));
emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
output_asm_insn (\"ldi\\t%3-1,%5\", operands);
output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands);
output_asm_insn (\"dbeq\\t%5,$1\", operands);
+ return \"\";
}")
(define_expand "cmpstrqi"
rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
rtx op1lo = operand_subword (operands[1], 0, 0, HImode);
- rtx count = gen_rtx (CONST_INT, VOIDmode,
- (INTVAL (operands[2]) - 32));
+ rtx count = gen_rtx_CONST_INT (VOIDmode, (INTVAL (operands[2]) - 32));
if (INTVAL (count))
emit_insn (gen_ashlqi3 (op0hi, op1lo, count));
rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
- rtx count = gen_rtx (CONST_INT, VOIDmode,
- (INTVAL (operands[2]) - 32));
+ rtx count = gen_rtx_CONST_INT (VOIDmode, (INTVAL (operands[2]) - 32));
if (INTVAL (count))
emit_insn (gen_lshrqi3 (op0lo, op1hi, count));
rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
- rtx count = gen_rtx (CONST_INT, VOIDmode,
- (INTVAL (operands[2]) - 32));
+ rtx count = gen_rtx_CONST_INT (VOIDmode, (INTVAL (operands[2]) - 32));
if (INTVAL (count))
emit_insn (gen_ashrqi3 (op0lo, op1hi, count));
else
emit_insn (gen_movqi (op0lo, op1hi));
- emit_insn (gen_ashrqi3 (op0hi, op1hi, gen_rtx (CONST_INT,
- VOIDmode, 31)));
+ emit_insn (gen_ashrqi3 (op0hi, op1hi,
+ gen_rtx_CONST_INT (VOIDmode, 31)));
DONE;
}
emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
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