enum insn_code code;
int i;
+ /* A common failure mode if register status is not correct in the RTL
+ is for this routine to be called with a REGNO we didn't expect to
+ save. That will cause us to write an insn with a (nil) SET_DEST
+ or SET_SRC. Instead of doing so and causing a crash later, check
+ for this common case and abort here instead. This will remove one
+ step in debugging such problems. */
+
+ if (regno_save_mem[regno] == 0)
+ abort ();
+
/* If INSN is a CALL_INSN, we must insert our insns before any
USE insns in front of the CALL_INSN. */
;; operand 3 is the offset for the source and destination pointers
;; operand 4 is the first value to be loaded
;; operand 5 is the register to hold the value (r4 or r5)
-;; Upon completion, r2 and r3 are unchanged
(define_expand "call_block_move"
[(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "r")
(match_dup 3)))
(use (reg:SI 2))
(use (reg:SI 3))
- (use (reg:SI 4))
- (use (reg:SI 5))
+ (use (match_dup 5))
(parallel [(call (mem:SI (match_operand 0 "" ""))
(const_int 0))
- (use (reg:SI 1))])
- (clobber (reg:SI 4))
- (clobber (reg:SI 5))]
+ (use (reg:SI 1))])]
""
"")
(set (reg:SI 6) (match_operand:SI 6 "immediate_operand" "i"))
(use (reg:SI 2))
(use (reg:SI 3))
- (use (reg:SI 4))
- (use (reg:SI 5))
+ (use (match_dup 5))
(use (reg:SI 6))
(parallel [(call (mem:SI (match_operand 0 "" ""))
(const_int 0))
- (use (reg:SI 1))])
- (clobber (reg:SI 4))
- (clobber (reg:SI 5))
- (clobber (reg:SI 6))]
+ (use (reg:SI 1))])]
""
"")
\f