+Mon Mar 22 16:18:27 1999 Nick Clifton <nickc@cygnus.com>
+
+ * config/arm/elf.h (VALID_MACHINE_DECL_ATTRIBUTE): Do not bother
+ passing ATTRIBUTES to arm_valid_machine_decl_attribute.
+
+ * config/arm/coff.h (VALID_MACHINE_DECL_ATTRIBUTE): Do not bother
+ passing ATTRIBUTES to arm_valid_machine_decl_attribute.
+
+ * config/arm/arm.h (DEFAULT_RTX_COSTS): Do not bother passing
+ OUTER_CODE to arm_rtx_costs - it is not used.
+ (arm_compare_fp): Delete declaration.
+ (FINAL_PRESCAN_INSN): Do not bother passing OPVEC or NOPERANDS to
+ arm_final_prescan_insn - they are not used.
+ (const_ok_for_op): Remove prototype.
+ (arm_rtx_costs): Fix prototype.
+ (arm_valid_machine_decl_attribute): Fix prototype.
+ (final_prescan_insn): Fix prototype.
+
+ * config/arm/arm.md: Remove references to arm_compare_fp.
+
+ * config/arm/arm.c (arm_compare_fp): Delete.
+ (const_ok_for_op): Make function static. Add prototype. Remove
+ mode parameter - it is unused.
+ (arm_rtx_costs): Remove outer_code parameter.
+ (reload_memory_operand): Declare mode parameter unused.
+ (power_of_two_operand): Declare mode parameter unused.
+ (equality_operator): Declare mode parameter unused.
+ (load_multiple_operation): Declare mode parameter unused.
+ (store_multiple_operation): Declare mode parameter unused.
+ (multi_register_push): Declare mode parameter unused.
+ (arm_valid_machine_decl_attribute): Remove attributes parameter -
+ it is unused.
+ (select_dominance_cc_mode): Remove op parameter - it is unused.
+ (gen_compare_reg): Remove fp parameter - it is unused.
+ (final_prescan_insn): Remove opvec and noperands parameters - they
+ are unused.
+
Mon Mar 22 14:35:28 1999 Nick Clifton <nickc@cygnus.com>
* tm.texi (MD_SCHED_INIT): Add missing closing parenthesis.
HOST_WIDE_INT, rtx, rtx, int, int));
static int arm_naked_function_p PROTO ((tree));
static void init_fpa_table PROTO ((void));
-static enum machine_mode select_dominance_cc_mode PROTO ((enum rtx_code, rtx,
- rtx, HOST_WIDE_INT));
+static enum machine_mode select_dominance_cc_mode PROTO ((rtx, rtx,
+ HOST_WIDE_INT));
static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
static void dump_table PROTO ((rtx));
static int fixit PROTO ((rtx, enum machine_mode, int));
static void emit_multi_reg_push PROTO ((int));
static void emit_sfm PROTO ((int, int));
static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
+static int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode));
/* Define the information needed to generate branch insns. This is
stored from the compare operation. */
rtx arm_compare_op0, arm_compare_op1;
-int arm_compare_fp;
/* What type of floating point are we tuning for? */
enum floating_point_type arm_fpu;
}
/* Return true if I is a valid constant for the operation CODE. */
-int
-const_ok_for_op (i, code, mode)
+static int
+const_ok_for_op (i, code)
HOST_WIDE_INT i;
enum rtx_code code;
- enum machine_mode mode;
{
if (const_ok_for_arm (i))
return 1;
|| (X) == arg_pointer_rtx)
int
-arm_rtx_costs (x, code, outer_code)
+arm_rtx_costs (x, code)
rtx x;
- enum rtx_code code, outer_code;
+ enum rtx_code code;
{
enum machine_mode mode = GET_MODE (x);
enum rtx_code subcode;
return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_INT
- && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
+ && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
? 0 : 8));
if (REG_OR_SUBREG_REG (XEXP (x, 0)))
return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_INT
- && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
+ && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
? 0 : 4));
else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
int
reload_memory_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
int regno = true_regnum (op);
int
power_of_two_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) == CONST_INT)
{
int equality_operator (x, mode)
rtx x;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return GET_CODE (x) == EQ || GET_CODE (x) == NE;
}
int
load_multiple_operation (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
HOST_WIDE_INT count = XVECLEN (op, 0);
int dest_regno;
int
store_multiple_operation (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
HOST_WIDE_INT count = XVECLEN (op, 0);
int src_regno;
int
multi_register_push (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) != PARALLEL
|| (GET_CODE (XVECEXP (op, 0, 0)) != SET)
to do the right thing. */
int
-arm_valid_machine_decl_attribute (decl, attributes, attr, args)
+arm_valid_machine_decl_attribute (decl, attr, args)
tree decl;
- tree attributes;
tree attr;
tree args;
{
}
static enum machine_mode
-select_dominance_cc_mode (op, x, y, cond_or)
- enum rtx_code op;
+select_dominance_cc_mode (x, y, cond_or)
rtx x;
rtx y;
HOST_WIDE_INT cond_or;
|| XEXP (x, 2) == const1_rtx)
&& GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
&& GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
- return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
+ return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
INTVAL (XEXP (x, 2)));
if (GET_MODE (x) == QImode && (op == EQ || op == NE))
floating point compare: I don't think that it is needed on the arm. */
rtx
-gen_compare_reg (code, x, y, fp)
+gen_compare_reg (code, x, y)
enum rtx_code code;
rtx x, y;
- int fp;
{
enum machine_mode mode = SELECT_CC_MODE (code, x, y);
rtx cc_reg = gen_rtx_REG (mode, 24);
void
-final_prescan_insn (insn, opvec, noperands)
+arm_final_prescan_insn (insn)
rtx insn;
- rtx *opvec;
- int noperands;
{
/* BODY will hold the body of INSN. */
register rtx body = PATTERN (insn);
|| (X) == arg_pointer_rtx)
#define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \
- return arm_rtx_costs (X, CODE, OUTER_CODE);
+ return arm_rtx_costs (X, CODE);
/* Moves to and from memory are quite expensive */
#define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
since it hasn't been defined! */
extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
-extern int arm_compare_fp;
/* Define the codes that are matched by predicates in arm.c */
#define PREDICATE_CODES \
we're optimising. Otherwise it's of no use anyway. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
if (optimize) \
- final_prescan_insn (INSN, OPVEC, NOPERANDS)
+ arm_final_prescan_insn (INSN)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
void arm_override_options PROTO ((void));
int use_return_insn PROTO ((int));
int const_ok_for_arm PROTO ((Hint));
-int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode, Mmode));
int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, Hint, Rtx, Rtx, int));
Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *));
int arm_return_in_memory PROTO ((Tree));
Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx));
int is_pic PROTO ((Rtx));
void arm_finalize_pic PROTO ((void));
-int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode, Rcode));
+int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode));
int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int));
int const_double_rtx_ok_for_fpu PROTO ((Rtx));
int neg_const_double_rtx_ok_for_fpu PROTO ((Rtx));
char * emit_ldm_seq PROTO ((Rtx *, int));
int store_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
char * emit_stm_seq PROTO ((Rtx *, int));
-int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree, Tree));
+int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree));
Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
int arm_gen_movstrqi PROTO ((Rtx *));
void output_func_epilogue STDIO_PROTO ((FILE *, int));
void arm_expand_prologue PROTO ((void));
void arm_print_operand STDIO_PROTO ((FILE *, Rtx, int));
-void final_prescan_insn PROTO ((Rtx, Rtx *, int));
+void arm_final_prescan_insn PROTO ((Rtx));
int short_branch PROTO ((int, int));
void assemble_align PROTO((int)); /* Used in arm.md, but defined in output.c */
int multi_register_push PROTO ((Rtx, Mmode));
{
arm_compare_op0 = operands[0];
arm_compare_op1 = operands[1];
- arm_compare_fp = 0;
DONE;
}
")
{
arm_compare_op0 = operands[0];
arm_compare_op1 = operands[1];
- arm_compare_fp = 1;
DONE;
}
")
{
arm_compare_op0 = operands[0];
arm_compare_op1 = operands[1];
- arm_compare_fp = 1;
DONE;
}
")
{
arm_compare_op0 = operands[0];
arm_compare_op1 = operands[1];
- arm_compare_fp = 1;
DONE;
}
")
""
"
{
- operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);
}
")
""
"
{
- operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);
}
")
"
{
enum rtx_code code = GET_CODE (operands[1]);
- rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
}")
|| (! fpu_add_operand (operands[3], SFmode)))
operands[3] = force_reg (SFmode, operands[3]);
- ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
}")
"
{
enum rtx_code code = GET_CODE (operands[1]);
- rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1,
- arm_compare_fp);
+ rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
}")
/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
is a valid machine specific attribute for DECL.
The attributes in ATTRIBUTES have previously been assigned to DECL. */
-extern int arm_valid_machine_decl_attribute ();
#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-arm_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
+arm_valid_machine_decl_attribute (DECL, IDENTIFIER, ARGS)
\f
/* This is COFF, but prefer stabs. */
#define SDB_DEBUGGING_INFO
/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
is a valid machine specific attribute for DECL.
The attributes in ATTRIBUTES have previously been assigned to DECL. */
-extern int arm_valid_machine_decl_attribute ();
#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-arm_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
+arm_valid_machine_decl_attribute (DECL, IDENTIFIER, ARGS)
\f
/* A C statement to output assembler commands which will identify the
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