* config/sparc/sparc.md (UNSPEC_EDGE8, UNSPEC_EDGE8L,

	UNSPEC_EDGE16, UNSPEC_EDGE16L, UNSPEC_EDGE32, UNSPEC_EDGE32L):
	New unspecs.
	(define_attr type): New type 'edge'.
	(edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis,
	edge32l_vis): New patterns.
	* config/sparc/ultra1_2.md: Add insn reservation for 'edge'.
	* config/sparc/ultra3.md: Likewise.
	* config/sparc/niagara.md: Likewise.
	* config/sparc/niagara2.md: Likewise.
	* config/sparc/sparc.d (sparc_vis_init_builtins): Generate
	builtins for VIS edge instructions.
	* config/sparc/visintrin.h (__vis_edge8, __vis_edge8l)
	(__vis_edge16, __vis_edge16l, __vis_edge32, __vis_edge32l): New
	intrinsics.
	(__v8qi, __v4qi): Make unsigned.
	(__vis_faligndatadi, ___vis_faligndatav2si, __vis_faligndatav4hi,
	__vis_faligndatav8qi, __vis_fmul8x16au, __vis_fmul8x16al,
	__vis_fpack32): Fix types.
	* doc/extend.texi: Document new 'edge' VIS intrinsics.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178931 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 007b8df..201d17c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,26 @@
+2011-09-17  David S. Miller  <davem@davemloft.net>
+
+       * config/sparc/sparc.md (UNSPEC_EDGE8, UNSPEC_EDGE8L,
+       UNSPEC_EDGE16, UNSPEC_EDGE16L, UNSPEC_EDGE32, UNSPEC_EDGE32L):
+       New unspecs.
+       (define_attr type): New type 'edge'.
+       (edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis,
+       edge32l_vis): New patterns.
+       * config/sparc/ultra1_2.md: Add insn reservation for 'edge'.
+       * config/sparc/ultra3.md: Likewise.
+       * config/sparc/niagara.md: Likewise.
+       * config/sparc/niagara2.md: Likewise.
+       * config/sparc/sparc.d (sparc_vis_init_builtins): Generate
+       builtins for VIS edge instructions.
+       * config/sparc/visintrin.h (__vis_edge8, __vis_edge8l)
+       (__vis_edge16, __vis_edge16l, __vis_edge32, __vis_edge32l): New
+       intrinsics.
+       (__v8qi, __v4qi): Make unsigned.
+       (__vis_faligndatadi, ___vis_faligndatav2si, __vis_faligndatav4hi,
+       __vis_faligndatav8qi, __vis_fmul8x16au, __vis_fmul8x16al,
+       __vis_fpack32): Fix types.
+       * doc/extend.texi: Document new 'edge' VIS intrinsics.
+
 2011-09-17  Jakub Jelinek  <jakub@redhat.com>
 
        * config/i386/sse.md (VIMAX_AVX2): Change V4DI to V2TI.

diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md
index e73c65b..a618b19 100644 (file)
--- a/gcc/config/sparc/niagara.md
+++ b/gcc/config/sparc/niagara.md
@@ -114,5 +114,5 @@
  */
 (define_insn_reservation "niag_vis" 8
   (and (eq_attr "cpu" "niagara")
-    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
+    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge"))
   "niag_pipe*8")

diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md
index 9d899f2..999e13b 100644 (file)
--- a/gcc/config/sparc/niagara2.md
+++ b/gcc/config/sparc/niagara2.md
@@ -86,5 +86,5 @@
 
 (define_insn_reservation "niag2_vis" 6
   (and (eq_attr "cpu" "niagara2,niagara3")
-    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
+    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge"))
   "niag2_pipe*6")

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index cf9e197..7e124a0 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -9169,6 +9169,20 @@ sparc_vis_init_builtins (void)
   /* Pixel distance.  */
   def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
               di_ftype_v8qi_v8qi_di);
+
+  /* Edge handling.  */
+  def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8_vis,
+               di_ftype_di_di);
+  def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8l_vis,
+               di_ftype_di_di);
+  def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16_vis,
+               di_ftype_di_di);
+  def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16l_vis,
+               di_ftype_di_di);
+  def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32_vis,
+               di_ftype_di_di);
+  def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32l_vis,
+               di_ftype_di_di);
 }
 
 /* Handle TARGET_EXPAND_BUILTIN target hook.

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 54cf620..483dea1 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -60,6 +60,12 @@
    (UNSPEC_ALIGNDATA           48)
    (UNSPEC_ALIGNADDR           49)
    (UNSPEC_PDIST               50)
+   (UNSPEC_EDGE8               51)
+   (UNSPEC_EDGE8L              52)
+   (UNSPEC_EDGE16              53)
+   (UNSPEC_EDGE16L             54)
+   (UNSPEC_EDGE32              55)
+   (UNSPEC_EDGE32L             56)
 
    (UNSPEC_SP_SET              60)
    (UNSPEC_SP_TEST             61)
@@ -142,7 +148,7 @@
    fpcmp,
    fpmul,fpdivs,fpdivd,
    fpsqrts,fpsqrtd,
-   fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,
+   fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,edge,
    cmove,
    ialuX,
    multi,savew,flushw,iflush,trap"
@@ -7803,4 +7809,72 @@
   [(set_attr "type" "fga")
    (set_attr "fptype" "double")])
 
+;; Edge instructions produce condition codes equivalent to a 'subcc'
+;; with the same operands.
+(define_insn "edge8_vis"
+  [(set (reg:CCX_NOOV 100)
+        (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
+                                   (match_operand:DI 2 "register_operand" "rJ"))
+                         (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8))]
+  "TARGET_VIS"
+  "edge8\t%r1, %r2, %0"
+  [(set_attr "type" "edge")])
+
+(define_insn "edge8l_vis"
+  [(set (reg:CCX_NOOV 100)
+        (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
+                                   (match_operand:DI 2 "register_operand" "rJ"))
+                         (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8L))]
+  "TARGET_VIS"
+  "edge8l\t%r1, %r2, %0"
+  [(set_attr "type" "edge")])
+
+(define_insn "edge16_vis"
+  [(set (reg:CCX_NOOV 100)
+        (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
+                                   (match_operand:DI 2 "register_operand" "rJ"))
+                         (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16))]
+  "TARGET_VIS"
+  "edge16\t%r1, %r2, %0"
+  [(set_attr "type" "edge")])
+
+(define_insn "edge16l_vis"
+  [(set (reg:CCX_NOOV 100)
+        (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
+                                   (match_operand:DI 2 "register_operand" "rJ"))
+                         (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16L))]
+  "TARGET_VIS"
+  "edge16l\t%r1, %r2, %0"
+  [(set_attr "type" "edge")])
+
+(define_insn "edge32_vis"
+  [(set (reg:CCX_NOOV 100)
+        (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
+                                   (match_operand:DI 2 "register_operand" "rJ"))
+                         (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32))]
+  "TARGET_VIS"
+  "edge32\t%r1, %r2, %0"
+  [(set_attr "type" "edge")])
+
+(define_insn "edge32l_vis"
+  [(set (reg:CCX_NOOV 100)
+        (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
+                                   (match_operand:DI 2 "register_operand" "rJ"))
+                         (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32L))]
+  "TARGET_VIS"
+  "edge32l\t%r1, %r2, %0"
+  [(set_attr "type" "edge")])
+
 (include "sync.md")

diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md
index f0bd7a1..a24cb81 100644 (file)
--- a/gcc/config/sparc/ultra1_2.md
+++ b/gcc/config/sparc/ultra1_2.md
@@ -94,7 +94,7 @@
 
 (define_insn_reservation "us1_simple_ieu1" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "compare"))
+    (eq_attr "type" "compare,edge"))
   "us1_ieu1 + us1_slot012")
 
 (define_insn_reservation "us1_ialuX" 1

diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md
index 8feaf79..d438812 100644 (file)
--- a/gcc/config/sparc/ultra3.md
+++ b/gcc/config/sparc/ultra3.md
@@ -36,7 +36,7 @@
 
 (define_insn_reservation "us3_single" 1
   (and (eq_attr "cpu" "ultrasparc3")
-    (eq_attr "type" "multi,savew,flushw,iflush,trap"))
+    (eq_attr "type" "multi,savew,flushw,iflush,trap,edge"))
   "us3_single_issue")
 
 (define_insn_reservation "us3_integer" 1

diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h
index 5687c9b..25d7bab 100644 (file)
--- a/gcc/config/sparc/visintrin.h
+++ b/gcc/config/sparc/visintrin.h
@@ -27,8 +27,8 @@
 typedef int __v2si __attribute__ ((__vector_size__ (8)));
 typedef short __v4hi __attribute__ ((__vector_size__ (8)));
 typedef short __v2hi __attribute__ ((__vector_size__ (4)));
-typedef char __v8qi __attribute__ ((__vector_size__ (8)));
-typedef char __v4qi __attribute__ ((__vector_size__ (4)));
+typedef unsigned char __v8qi __attribute__ ((__vector_size__ (8)));
+typedef unsigned char __v4qi __attribute__ ((__vector_size__ (4)));
 typedef int __i64 __attribute__ ((__mode__ (DI)));
 
 extern __inline void *
@@ -40,30 +40,30 @@ __vis_alignaddr (void *__A, long __B)
 
 extern __inline __i64
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_faligndatadi (__i64 __A)
+__vis_faligndatadi (__i64 __A, __i64 __B)
 {
-  return __builtin_vis_faligndatadi (__A);
+  return __builtin_vis_faligndatadi (__A, __B);
 }
 
 extern __inline __v2si
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_faligndatav2si (__v2si __A)
+__vis_faligndatav2si (__v2si __A, __v2si __B)
 {
-  return __builtin_vis_faligndatav2si (__A);
+  return __builtin_vis_faligndatav2si (__A, __B);
 }
 
 extern __inline __v4hi
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_faligndatav4hi (__v4hi __A)
+__vis_faligndatav4hi (__v4hi __A, __v4hi __B)
 {
-  return __builtin_vis_faligndatav4hi (__A);
+  return __builtin_vis_faligndatav4hi (__A, __B);
 }
 
 extern __inline __v8qi
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_faligndatav8qi (__v8qi __A)
+__vis_faligndatav8qi (__v8qi __A, __v8qi __B)
 {
-  return __builtin_vis_faligndatav8qi (__A);
+  return __builtin_vis_faligndatav8qi (__A, __B);
 }
 
 extern __inline __v4hi
@@ -82,14 +82,14 @@ __vis_fmul8x16 (__v4qi __A, __v4hi __B)
 
 extern __inline __v4hi
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_fmul8x16au (__v4qi __A, __v4hi __B)
+__vis_fmul8x16au (__v4qi __A, __v2hi __B)
 {
   return __builtin_vis_fmul8x16au (__A, __B);
 }
 
 extern __inline __v4hi
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_fmul8x16al (__v4qi __A, __v4hi __B)
+__vis_fmul8x16al (__v4qi __A, __v2hi __B)
 {
   return __builtin_vis_fmul8x16al (__A, __B);
 }
@@ -131,7 +131,7 @@ __vis_fpack16 (__v4hi __A)
 
 extern __inline __v8qi
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-__vis_fpack32 (__v2si __A, __v2si __B)
+__vis_fpack32 (__v2si __A, __v8qi __B)
 {
   return __builtin_vis_fpack32 (__A, __B);
 }
@@ -157,4 +157,46 @@ __vis_pdist (__v8qi __A, __v8qi __B, __i64 __C)
   return __builtin_vis_pdist (__A, __B, __C);
 }
 
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_edge8 (__i64 __A, __i64 __B)
+{
+  return __builtin_vis_edge8 (__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_edge8l (__i64 __A, __i64 __B)
+{
+  return __builtin_vis_edge8l (__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_edge16 (__i64 __A, __i64 __B)
+{
+  return __builtin_vis_edge16 (__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_edge16l (__i64 __A, __i64 __B)
+{
+  return __builtin_vis_edge16l (__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_edge32 (__i64 __A, __i64 __B)
+{
+  return __builtin_vis_edge32 (__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_edge32l (__i64 __A, __i64 __B)
+{
+  return __builtin_vis_edge32l (__A, __B);
+}
+
 #endif  /* _VISINTRIN_H_INCLUDED */

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 0b36336..75f4874 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -12957,6 +12957,13 @@ v2hi __builtin_vis_fpackfix (v2si);
 v8qi __builtin_vis_fpmerge (v4qi, v4qi);
 
 int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t);
+
+int64_t __builtin_vis_edge8 (int64_t, int64_t);
+int64_t __builtin_vis_edge8l (int64_t, int64_t);
+int64_t __builtin_vis_edge16 (int64_t, int64_t);
+int64_t __builtin_vis_edge16l (int64_t, int64_t);
+int64_t __builtin_vis_edge32 (int64_t, int64_t);
+int64_t __builtin_vis_edge32l (int64_t, int64_t);
 @end smallexample
 
 @node SPU Built-in Functions