i965/gen7: fix encoding of (huge) surface size for BRW_SURFACE_BUFFER

i965/gen7: fix encoding of (huge) surface size for BRW_SURFACE_BUFFER

Unlike GEN6, the bits of entry count are distributed like this

  width  = (entry_count & 0x0000007f);       /* bits [6:0] */
  height = (entry_count & 0x001fff80) >> 7;  /* bits [20:7] */
  depth  = (entry_count & 0x7fe00000) >> 21; /* bits [30:21] */

The maximum entry count is still limited to 2^27.

This was noted while going over the PRM.  No test is impacted, because
1<<20 (the bit that moved) is much larger than GL_UNIFORM_BLOCK_MAX_SIZE,
GL_MAX_TEXTURE_BUFFER_SIZE, or MAX_*_UNIFORM_COMPONENTS.

v2: Explain more in the commit message (by anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>