THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
- Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
+ 2008 Free Software Foundation, Inc.
- This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of libopcodes.
- This program is free software; you can redistribute it and/or modify
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
{
unsigned long maxval = mask;
-
- if ((unsigned long) value > maxval)
+ unsigned long val = (unsigned long) value;
+
+ /* For hosts with a word size > 32 check to see if value has been sign
+ extended beyond 32 bits. If so then ignore these higher sign bits
+ as the user is attempting to store a 32-bit signed value into an
+ unsigned 32-bit field which is allowed. */
+ if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
+ val &= 0xFFFFFFFF;
+
+ if (val > maxval)
{
/* xgettext:c-format */
sprintf (errbuf,
- _("operand out of range (%lu not between 0 and %lu)"),
- value, maxval);
+ _("operand out of range (0x%lx not between 0 and 0x%lx)"),
+ val, maxval);
return errbuf;
}
}
word_length may be too big. */
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
{
- if (word_offset == 0
- && word_length > total_length)
- word_length = total_length;
+ if (word_offset + word_length > total_length)
+ word_length = total_length - word_offset;
}
/* Does the value reside in INSN_VALUE, and at the right alignment? */
case M32C_OPERAND_BIT16RN :
errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer);
break;
+ case M32C_OPERAND_BIT3_S :
+ {
+{
+ FLD (f_7_1) = ((((FLD (f_imm3_S)) - (1))) & (1));
+ FLD (f_2_2) = ((((unsigned int) (((FLD (f_imm3_S)) - (1))) >> (1))) & (3));
+}
+ errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer);
break;
errmsg = insert_normal (cd, value, 0, 32, 8, 16, 32, total_length, buffer);
}
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ {
+ long value = fields->f_dsp_40_u20;
+ value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (983040))));
+ errmsg = insert_normal (cd, value, 0, 32, 8, 20, 32, total_length, buffer);
+ }
+ break;
case M32C_OPERAND_DSP_40_U24 :
{
long value = fields->f_dsp_40_u24;
errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer);
}
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ {
+{
+ FLD (f_dsp_64_u8) = ((((unsigned int) (FLD (f_dsp_48_u20)) >> (16))) & (15));
+ FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_u20)) & (65535));
+}
+ {
+ long value = fields->f_dsp_48_u16;
+ value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))));
+ errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer);
+ }
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case M32C_OPERAND_DSP_48_U24 :
{
{
case M32C_OPERAND_DSP_48_U8 :
errmsg = insert_normal (cd, fields->f_dsp_48_u8, 0, 32, 16, 8, 32, total_length, buffer);
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ {
+ long value = fields->f_dsp_8_s24;
+ value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((EXTQISI (TRUNCSIQI (((value) & (255))))) << (16))));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 24, 32, total_length, buffer);
+ }
+ break;
case M32C_OPERAND_DSP_8_S8 :
errmsg = insert_normal (cd, fields->f_dsp_8_s8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
break;
case M32C_OPERAND_IMM_12_S4 :
errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
+ break;
case M32C_OPERAND_IMM_13_U3 :
errmsg = insert_normal (cd, fields->f_imm_13_u3, 0, 0, 13, 3, 32, total_length, buffer);
break;
case M32C_OPERAND_IMM_8_S4 :
errmsg = insert_normal (cd, fields->f_imm_8_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, buffer);
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ errmsg = insert_normal (cd, fields->f_imm_8_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, buffer);
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
break;
case M32C_OPERAND_BIT16RN :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn);
break;
+ case M32C_OPERAND_BIT3_S :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1);
+ if (length <= 0) break;
+{
+ FLD (f_imm3_S) = ((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (1));
+}
+ }
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed);
break;
fields->f_dsp_40_u16 = value;
}
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 20, 32, total_length, pc, & value);
+ value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (983040))));
+ fields->f_dsp_40_u20 = value;
+ }
+ break;
case M32C_OPERAND_DSP_40_U24 :
{
long value;
fields->f_dsp_48_u16 = value;
}
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ {
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value);
+ value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))));
+ fields->f_dsp_48_u16 = value;
+ }
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8);
+ if (length <= 0) break;
+{
+ FLD (f_dsp_48_u20) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u8)) << (16))) & (983040))));
+}
+ }
+ break;
case M32C_OPERAND_DSP_48_U24 :
{
{
case M32C_OPERAND_DSP_48_U8 :
length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 8, 32, total_length, pc, & fields->f_dsp_48_u8);
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 24, 32, total_length, pc, & value);
+ value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((EXTQISI (TRUNCSIQI (((value) & (255))))) << (16))));
+ fields->f_dsp_8_s24 = value;
+ }
+ break;
case M32C_OPERAND_DSP_8_S8 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_dsp_8_s8);
break;
case M32C_OPERAND_IMM_12_S4 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
+ break;
case M32C_OPERAND_IMM_13_U3 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_imm_13_u3);
break;
case M32C_OPERAND_IMM_8_S4 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, pc, & fields->f_imm_8_s4);
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, pc, & fields->f_imm_8_s4);
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
break;
case M32C_OPERAND_BIT16RN :
value = fields->f_dst16_rn;
break;
+ case M32C_OPERAND_BIT3_S :
+ value = fields->f_imm3_S;
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
value = fields->f_dst32_an_prefixed;
break;
case M32C_OPERAND_DSP_40_U16 :
value = fields->f_dsp_40_u16;
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ value = fields->f_dsp_40_u20;
+ break;
case M32C_OPERAND_DSP_40_U24 :
value = fields->f_dsp_40_u24;
break;
case M32C_OPERAND_DSP_48_U16 :
value = fields->f_dsp_48_u16;
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ value = fields->f_dsp_48_u20;
+ break;
case M32C_OPERAND_DSP_48_U24 :
value = fields->f_dsp_48_u24;
break;
case M32C_OPERAND_DSP_48_U8 :
value = fields->f_dsp_48_u8;
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ value = fields->f_dsp_8_s24;
+ break;
case M32C_OPERAND_DSP_8_S8 :
value = fields->f_dsp_8_s8;
break;
case M32C_OPERAND_IMM_12_S4 :
value = fields->f_imm_12_s4;
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ value = fields->f_imm_12_s4;
+ break;
case M32C_OPERAND_IMM_13_U3 :
value = fields->f_imm_13_u3;
break;
case M32C_OPERAND_IMM_8_S4 :
value = fields->f_imm_8_s4;
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ value = fields->f_imm_8_s4;
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
value = fields->f_imm_12_s4;
break;
case M32C_OPERAND_BIT16RN :
value = fields->f_dst16_rn;
break;
+ case M32C_OPERAND_BIT3_S :
+ value = fields->f_imm3_S;
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
value = fields->f_dst32_an_prefixed;
break;
case M32C_OPERAND_DSP_40_U16 :
value = fields->f_dsp_40_u16;
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ value = fields->f_dsp_40_u20;
+ break;
case M32C_OPERAND_DSP_40_U24 :
value = fields->f_dsp_40_u24;
break;
case M32C_OPERAND_DSP_48_U16 :
value = fields->f_dsp_48_u16;
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ value = fields->f_dsp_48_u20;
+ break;
case M32C_OPERAND_DSP_48_U24 :
value = fields->f_dsp_48_u24;
break;
case M32C_OPERAND_DSP_48_U8 :
value = fields->f_dsp_48_u8;
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ value = fields->f_dsp_8_s24;
+ break;
case M32C_OPERAND_DSP_8_S8 :
value = fields->f_dsp_8_s8;
break;
case M32C_OPERAND_IMM_12_S4 :
value = fields->f_imm_12_s4;
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ value = fields->f_imm_12_s4;
+ break;
case M32C_OPERAND_IMM_13_U3 :
value = fields->f_imm_13_u3;
break;
case M32C_OPERAND_IMM_8_S4 :
value = fields->f_imm_8_s4;
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ value = fields->f_imm_8_s4;
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
value = fields->f_imm_12_s4;
break;
case M32C_OPERAND_BIT16RN :
fields->f_dst16_rn = value;
break;
+ case M32C_OPERAND_BIT3_S :
+ fields->f_imm3_S = value;
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
fields->f_dst32_an_prefixed = value;
break;
case M32C_OPERAND_DSP_40_U16 :
fields->f_dsp_40_u16 = value;
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ fields->f_dsp_40_u20 = value;
+ break;
case M32C_OPERAND_DSP_40_U24 :
fields->f_dsp_40_u24 = value;
break;
case M32C_OPERAND_DSP_48_U16 :
fields->f_dsp_48_u16 = value;
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ fields->f_dsp_48_u20 = value;
+ break;
case M32C_OPERAND_DSP_48_U24 :
fields->f_dsp_48_u24 = value;
break;
case M32C_OPERAND_DSP_48_U8 :
fields->f_dsp_48_u8 = value;
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ fields->f_dsp_8_s24 = value;
+ break;
case M32C_OPERAND_DSP_8_S8 :
fields->f_dsp_8_s8 = value;
break;
case M32C_OPERAND_IMM_12_S4 :
fields->f_imm_12_s4 = value;
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ fields->f_imm_12_s4 = value;
+ break;
case M32C_OPERAND_IMM_13_U3 :
fields->f_imm_13_u3 = value;
break;
case M32C_OPERAND_IMM_8_S4 :
fields->f_imm_8_s4 = value;
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ fields->f_imm_8_s4 = value;
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
fields->f_imm_12_s4 = value;
break;
case M32C_OPERAND_BIT16RN :
fields->f_dst16_rn = value;
break;
+ case M32C_OPERAND_BIT3_S :
+ fields->f_imm3_S = value;
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
fields->f_dst32_an_prefixed = value;
break;
case M32C_OPERAND_DSP_40_U16 :
fields->f_dsp_40_u16 = value;
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ fields->f_dsp_40_u20 = value;
+ break;
case M32C_OPERAND_DSP_40_U24 :
fields->f_dsp_40_u24 = value;
break;
case M32C_OPERAND_DSP_48_U16 :
fields->f_dsp_48_u16 = value;
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ fields->f_dsp_48_u20 = value;
+ break;
case M32C_OPERAND_DSP_48_U24 :
fields->f_dsp_48_u24 = value;
break;
case M32C_OPERAND_DSP_48_U8 :
fields->f_dsp_48_u8 = value;
break;
+ case M32C_OPERAND_DSP_8_S24 :
+ fields->f_dsp_8_s24 = value;
+ break;
case M32C_OPERAND_DSP_8_S8 :
fields->f_dsp_8_s8 = value;
break;
case M32C_OPERAND_IMM_12_S4 :
fields->f_imm_12_s4 = value;
break;
+ case M32C_OPERAND_IMM_12_S4N :
+ fields->f_imm_12_s4 = value;
+ break;
case M32C_OPERAND_IMM_13_U3 :
fields->f_imm_13_u3 = value;
break;
case M32C_OPERAND_IMM_8_S4 :
fields->f_imm_8_s4 = value;
break;
+ case M32C_OPERAND_IMM_8_S4N :
+ fields->f_imm_8_s4 = value;
+ break;
case M32C_OPERAND_IMM_SH_12_S4 :
fields->f_imm_12_s4 = value;
break;
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