/* Conditional constant propagation pass for the GNU compiler.
- Copyright (C) 2000,2001 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
Original framework by Daniel Berlin <dan@cgsoftware.com>
Fleshed out and major cleanups by Jeff Law <law@redhat.com>
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-GNU CC is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
-
+
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to the Free
+along with GCC; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
5. Another simple SSA DCE pass to remove dead code exposed
by CCP.
- When we exit, we are still in SSA form.
+ When we exit, we are still in SSA form.
Potential further enhancements:
VARYING
} latticevalue;
-/* Main structure for CCP.
+/* Main structure for CCP.
Contains the lattice value and, if it's a constant, the constant
value. */
/* Simple macros to simplify code */
#define SSA_NAME(x) REGNO (SET_DEST (x))
-#define PHI_PARMS(x) XVEC (SET_SRC (x), 0)
#define EIE(x,y) EDGE_INDEX (edges, x, y)
static void visit_phi_node PARAMS ((rtx, basic_block));
/* If the current value of PHI_NODE is UNDEFINED and one
node in PHI_NODE is CONSTANT, then the new value of the
PHI is that CONSTANT. Note this can turn into VARYING
- if we find another distinct constant later. */
+ if we find another distinct constant later. */
if (phi_node_lattice_val == UNDEFINED
&& phi_node_expr == NULL
&& current_parm_lattice_val == CONSTANT)
}
}
-/* Go through the expression, call the approriate evaluation routines
+/* Go through the expression, call the appropriate evaluation routines
to attempt cprop */
static void
visit_expression (insn, block)
}
/* Hard registers are not put in SSA form and thus we must consider
- them varying. All the more reason to avoid hard registers in
+ them varying. All the more reason to avoid hard registers in
RTL until as late as possible in the compilation. */
if (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
{
rtx simplified = NULL;
/* We've got some kind of INSN. If it's simple, try to evaluate
- it and record the results.
+ it and record the results.
We already know this insn is a single_set and that it sets
a pseudo register. So we just need to extract the source
defs_to_undefined (insn);
break;
}
-
+
/* Simplify source operands to whatever known values they
may have. */
if (GET_CODE (src0) == REG
defs_to_undefined (insn);
break;
}
-
+
/* Simplify source operands to whatever known values they
may have. */
if (GET_CODE (src0) == REG
defs_to_undefined (insn);
break;
}
-
+
/* Simplify source operands to whatever known values they
may have. */
if (GET_CODE (src0) == REG
src0, src1, src2);
break;
}
-
+
default:
defs_to_varying (insn);
}
values[REGNO (dest)].const_value = simplified;
}
else
- defs_to_varying (insn);
+ defs_to_varying (insn);
}
}
/* Iterate over the FLOW_EDGES work list. Simulate the target block
for each edge. */
static void
-examine_flow_edges (void)
+examine_flow_edges ()
{
while (flow_edges != NULL)
{
currinsn = NEXT_INSN (currinsn);
}
-
+
/* Don't forget the last insn in the block. */
if (INSN_P (currinsn))
visit_expression (currinsn, succ_block);
-
+
/* If we haven't looked at the next block, and it has a
single successor, add it onto the worklist. This is because
if we only have one successor, we know it gets executed,
- so we don't have to wait for cprop to tell us. */
+ so we don't have to wait for cprop to tell us. */
if (succ_edge != NULL
&& succ_edge->succ_next == NULL
&& !TEST_BIT (executable_edges,
/* Pick an entry off the worklist (it does not matter which
entry we pick). */
- member = sbitmap_first_set_bit (ssa_edges);
+ member = sbitmap_first_set_bit (ssa_edges);
RESET_BIT (ssa_edges, member);
/* Iterate through all the uses of this entry. */
{
if (TEST_BIT (executable_blocks, BLOCK_NUM (useinsn)))
visit_phi_node (useinsn, BLOCK_FOR_INSN (useinsn));
- }
+ }
else
{
if (TEST_BIT (executable_blocks, BLOCK_NUM (useinsn)))
}
/* Examine each edge to see if we were able to prove any were
- not executable.
+ not executable.
If an edge is not executable, then we can remove its alternative
in PHI nodes as the destination of the edge, we can simplify the
sbitmap executable_edges;
{
int i;
+ basic_block bb;
for (i = 0; i < NUM_EDGES (edges); i++)
{
remove_phi_alternative (PATTERN (insn), edge->src);
if (rtl_dump_file)
fprintf (rtl_dump_file,
- "Removing alternative for bb %d of phi %d\n",
+ "Removing alternative for bb %d of phi %d\n",
edge->src->index, SSA_NAME (PATTERN (insn)));
insn = NEXT_INSN (insn);
}
In cases B & C we are removing uses of registers, so make sure
to note those changes for the DF analyzer. */
- for (i = 0; i < n_basic_blocks; i++)
+ FOR_EACH_BB (bb)
{
- basic_block bb = BASIC_BLOCK (i);
rtx insn = bb->end;
edge edge = bb->succ;
}
}
}
-
+
/* Perform substitution of known values for pseudo registers.
??? Note we do not do simplifications or constant folding here, it
anyway. Consider that if the simplification would result in an
expression that produces a constant value that the value would
have been discovered and recorded already.
-
+
We perform two transformations. First, we initialize pseudos to their
known constant values at their definition point. Second, we try to
replace uses with the known constant value. */
/* Do not try to simplify PHI nodes down to a constant load.
That will be done later as we translate out of SSA. Also,
doing that here could violate the rule that all PHI nodes
- are consecutive at the start of the basic block. */
- if (! PHI_NODE_P (def))
+ are consecutive at the start of the basic block.
+
+ Don't do anything to nodes that were already sets to
+ constants. */
+ if (! PHI_NODE_P (def)
+ && ! ((GET_CODE (def) == INSN
+ && GET_CODE (SET_SRC (set)) == CONST_INT)))
{
if (rtl_dump_file)
fprintf (rtl_dump_file,
&& (GET_CODE (useinsn) == INSN
|| GET_CODE (useinsn) == JUMP_INSN))
{
-
+
if (validate_replace_src (regno_reg_rtx [i],
values[i].const_value,
useinsn))
{
if (rtl_dump_file)
- fprintf (rtl_dump_file,
+ fprintf (rtl_dump_file,
"Register %d in insn %d replaced with constant\n",
i, INSN_UID (useinsn));
INSN_CODE (useinsn) = -1;
BLOCK_FOR_INSN (useinsn),
useinsn);
}
-
+
}
}
}
static void
ssa_ccp_df_delete_unreachable_insns ()
{
- int i;
+ basic_block b;
/* Use the CFG to find all the reachable blocks. */
find_unreachable_blocks ();
/* Now we know what blocks are not reachable. Mark all the insns
in those blocks as deleted for the DF analyzer. We'll let the
normal flow code actually remove the unreachable blocks. */
- for (i = n_basic_blocks - 1; i >= 0; --i)
+ FOR_EACH_BB_REVERSE (b)
{
- basic_block b = BASIC_BLOCK (i);
-
- if (b->aux != NULL)
- /* This block was found. Tidy up the mark. */
- b->aux = NULL;
- else
+ if (!(b->flags & BB_REACHABLE))
{
rtx start = b->head;
rtx end = b->end;
operate on so that it can be called for sub-graphs. */
void
-ssa_const_prop (void)
+ssa_const_prop ()
{
unsigned int i;
edge curredge;
df_analyse (df_analyzer, 0,
DF_RD_CHAIN | DF_RU_CHAIN | DF_REG_INFO | DF_HARD_REGS);
- /* We need mappings from insn to its containing block. */
- compute_bb_for_insn (get_max_uid ());
-
/* Perform a quick and dirty dead code elimination pass. This is not
as aggressive as it could be, but it's good enough to clean up a
lot of unwanted junk and it is fast. */
for (i = 0; i < VARRAY_SIZE (ssa_definition); i++)
{
if (i < FIRST_PSEUDO_REGISTER)
- values[i].lattice_val = VARYING;
+ values[i].lattice_val = VARYING;
else
values[i].lattice_val = UNDEFINED;
values[i].const_value = NULL;
ssa_edges = sbitmap_alloc (VARRAY_SIZE (ssa_definition));
sbitmap_zero (ssa_edges);
- executable_blocks = sbitmap_alloc (n_basic_blocks);
+ executable_blocks = sbitmap_alloc (last_basic_block);
sbitmap_zero (executable_blocks);
executable_edges = sbitmap_alloc (NUM_EDGES (edges));
sbitmap_free (executable_blocks);
executable_blocks = NULL;
+ sbitmap_free (ssa_edges);
+ ssa_edges = NULL;
+
free_edge_list (edges);
edges = NULL;
void *data;
{
rtx x = *current_rtx;
- sbitmap worklist = (sbitmap)data;
+ sbitmap worklist = (sbitmap) data;
if (x == NULL_RTX)
return 0;
== NOTE_INSN_DELETED))
|| side_effects_p (PATTERN (VARRAY_RTX (ssa_definition, reg))))
continue;
-
+
/* Iterate over the uses of this register. If we can not find
any uses that have not been deleted, then the definition of
this register is dead. */
/* If we did not find a use of this register, then the definition
of this register is dead. */
-
+
if (! found_use)
{
rtx def = VARRAY_RTX (ssa_definition, reg);
deleted. */
df_insn_delete (df, BLOCK_FOR_INSN (def), def);
- if (PHI_NODE_P (def))
- {
- if (def == BLOCK_FOR_INSN (def)->head
- && def == BLOCK_FOR_INSN (def)->end)
- {
- /* Delete it. */
- PUT_CODE (def, NOTE);
- NOTE_LINE_NUMBER (def) = NOTE_INSN_DELETED;
- }
- else if (def == BLOCK_FOR_INSN (def)->head)
- {
- BLOCK_FOR_INSN (def)->head = NEXT_INSN (def);
- flow_delete_insn (def);
- }
- else if (def == BLOCK_FOR_INSN (def)->end)
- {
- BLOCK_FOR_INSN (def)->end = PREV_INSN (def);
- flow_delete_insn (def);
- }
- else
- flow_delete_insn (def);
- }
- else
- {
- flow_delete_insn (def);
- }
VARRAY_RTX (ssa_definition, reg) = NULL;
}
}
sbitmap_free (worklist);
+
+ /* Update the use-def chains in the df_analyzer as needed. */
+ df_analyse (df_analyzer, 0,
+ DF_RD_CHAIN | DF_RU_CHAIN | DF_REG_INFO | DF_HARD_REGS);
}
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