-@c Copyright (C) 1988, 89, 92, 94, 97, 1998 Free Software Foundation, Inc.
+@c Copyright (C) 1988, 89, 92, 94, 97, 1998, 1999, 2000 Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@menu
* RTL Objects:: Expressions vs vectors vs strings vs integers.
+* RTL Classes:: Categories of RTL expresion objects, and their structure.
* Accessors:: Macros to access expression operands or vector elts.
* Flags:: Other flags in an RTL expression.
* Machine Modes:: Describing the size and format of a datum.
* Arithmetic:: Expressions representing arithmetic on other expressions.
* Comparisons:: Expressions representing comparison of expressions.
* Bit Fields:: Expressions representing bitfields in memory or reg.
+* Vector Operations:: Expressions involving vector datatypes.
* Conversions:: Extending, truncating, floating or fixing.
* RTL Declarations:: Declaring volatility, constancy, etc.
* Side Effects:: Expressions for storing in registers, etc.
* Reading RTL:: Reading textual RTL from a file.
@end menu
-@node RTL Objects, Accessors, RTL, RTL
+@node RTL Objects
@section RTL Object Types
@cindex RTL object types
In a few contexts a null pointer is valid where an expression is normally
wanted. The written form of this is @code{(nil)}.
-@node Accessors, Flags, RTL Objects, RTL
-@section Access to Operands
-@cindex accessors
-@cindex access to operands
-@cindex operand access
+@node RTL Classes
+@section RTL Classes and Formats
+@cindex RTL classes
+@cindex classes of RTX codes
+@cindex RTX codes, classes of
+@findex GET_RTX_CLASS
+
+The various expression codes are divided into several @dfn{classes},
+which are represented by single characters. You can determine the class
+of an RTX code with the macro @code{GET_RTX_CLASS (@var{code})}.
+Currently, @file{rtx.def} defines these classes:
+
+@table @code
+@item o
+An RTX code that represents an actual object, such as a register
+(@code{REG}) or a memory location (@code{MEM}, @code{SYMBOL_REF}).
+Constants and basic transforms on objects (@code{ADDRESSOF},
+@code{HIGH}, @code{LO_SUM}) are also included. Note that @code{SUBREG}
+and @code{STRICT_LOW_PART} are not in this class, but in class @code{x}.
+
+@item <
+An RTX code for a comparison, such as @code{NE} or @code{LT}.
+
+@item 1
+An RTX code for a unary arithmetic operation, such as @code{NEG},
+@code{NOT}, or @code{ABS}. This category also includes value extension
+(sign or zero) and conversions between integer and floating point.
+
+@item c
+An RTX code for a commutative binary operation, such as @code{PLUS} or
+@code{AND}. @code{NE} and @code{EQ} are comparisons, so they have class
+@code{<}.
+
+@item 2
+An RTX code for a non-commutative binary operation, such as @code{MINUS},
+@code{DIV}, or @code{ASHIFTRT}.
+
+@item b
+An RTX code for a bitfield operation. Currently only
+@code{ZERO_EXTRACT} and @code{SIGN_EXTRACT}. These have three inputs
+and are lvalues (so they can be used for insertion as well). @xref{Bit
+Fields}.
+
+@item 3
+An RTX code for other three input operations. Currently only
+@code{IF_THEN_ELSE}.
+
+@item i
+An RTX code for an entire instruction: @code{INSN}, @code{JUMP_INSN}, and
+@code{CALL_INSN}. @xref{Insns}.
+
+@item m
+An RTX code for something that matches in insns, such as
+@code{MATCH_DUP}. These only occur in machine descriptions.
+
+@item a
+An RTX code for an auto-increment addressing mode, such as
+@code{POST_INC}.
+
+@item x
+All other RTX codes. This category includes the remaining codes used
+only in machine descriptions (@code{DEFINE_*}, etc.). It also includes
+all the codes describing side effects (@code{SET}, @code{USE},
+@code{CLOBBER}, etc.) and the non-insns that may appear on an insn
+chain, such as @code{NOTE}, @code{BARRIER}, and @code{CODE_LABEL}.
+@end table
@cindex RTL format
For each expression type @file{rtl.def} specifies the number of
expression (actually a pointer to an expression), @samp{i} for integer,
@samp{w} for wide integer, @samp{s} for string, and @samp{E} for vector
of expressions. The sequence of letters for an expression code is
-called its @dfn{format}. Thus, the format of @code{subreg} is
+called its @dfn{format}. For example, the format of @code{subreg} is
@samp{ei}.@refill
@cindex RTL format characters
special ways by small parts of the compiler.
@end table
-There are macros to get the number of operands, the format, and the
-class of an expression code:
+There are macros to get the number of operands and the format
+of an expression code:
@table @code
@findex GET_RTX_LENGTH
@findex GET_RTX_FORMAT
@item GET_RTX_FORMAT (@var{code})
The format of an RTX of code @var{code}, as a C string.
+@end table
-@findex GET_RTX_CLASS
-@cindex classes of RTX codes
-@item GET_RTX_CLASS (@var{code})
-A single character representing the type of RTX operation that code
-@var{code} performs.
-
-The following classes are defined:
+Some classes of RTX codes always have the same format. For example, it
+is safe to assume that all comparison operations have format @code{ee}.
@table @code
-@item o
-An RTX code that represents an actual object, such as @code{reg} or
-@code{mem}. @code{subreg} is not in this class.
-
-@item <
-An RTX code for a comparison. The codes in this class are
-@code{NE}, @code{EQ}, @code{LE}, @code{LT}, @code{GE}, @code{GT},
-@code{LEU}, @code{LTU}, @code{GEU}, @code{GTU}.@refill
-
@item 1
-An RTX code for a unary arithmetic operation, such as @code{neg}.
-
-@item c
-An RTX code for a commutative binary operation, other than @code{NE}
-and @code{EQ} (which have class @samp{<}).
+All codes of this class have format @code{e}.
-@item 2
-An RTX code for a noncommutative binary operation, such as @code{MINUS}.
+@item <
+@itemx c
+@itemx 2
+All codes of these classes have format @code{ee}.
@item b
-An RTX code for a bitfield operation, either @code{ZERO_EXTRACT} or
-@code{SIGN_EXTRACT}.
-
-@item 3
-An RTX code for other three input operations, such as @code{IF_THEN_ELSE}.
+@itemx 3
+All codes of these classes have format @code{eee}.
@item i
-An RTX code for a machine insn (@code{INSN}, @code{JUMP_INSN}, and
-@code{CALL_INSN}).@refill
-
-@item m
-An RTX code for something that matches in insns, such as @code{MATCH_DUP}.
+All codes of this class have formats that begin with @code{iuueiee}.
+@xref{Insns}. Note that not all RTL objects linked onto an insn chain
+are of class @code{i}.
-@item x
-All other RTX codes.
-@end table
+@item o
+@itemx m
+@itemx x
+You can make no assumptions about the format of these codes.
@end table
+@node Accessors
+@section Access to Operands
+@cindex accessors
+@cindex access to operands
+@cindex operand access
+
@findex XEXP
@findex XINT
@findex XWINT
can be used to assign the operands, lengths and vector elements as well as
to access them.
-@node Flags, Machine Modes, Accessors, RTL
+@node Flags
@section Flags in an RTL Expression
@cindex flags in RTL expression
@cindex @code{in_struct}, in @code{mem}
@cindex @samp{/s} in RTL dump
@item MEM_IN_STRUCT_P (@var{x})
-In @code{mem} expressions, nonzero for reference to an entire
-structure, union or array, or to a component of one. Zero for
-references to a scalar variable or through a pointer to a scalar.
-Stored in the @code{in_struct} field and printed as @samp{/s}.
+In @code{mem} expressions, nonzero for reference to an entire structure,
+union or array, or to a component of one. Zero for references to a
+scalar variable or through a pointer to a scalar. Stored in the
+@code{in_struct} field and printed as @samp{/s}. If both this flag and
+MEM_SCALAR_P are clear, then we don't know whether this MEM is in a
+structure or not. Both flags should never be simultaneously set.
+
+@findex MEM_SCALAR_P
+@cindex @code{mem} and @samp{/f}
+@cindex @code{frame_related}, in@code{mem}
+@cindex @samp{/f} in RTL dump
+@item MEM_SCALAR_P (@var{x})
+In @code{mem} expressions, nonzero for reference to a scalar known not
+to be a member of a structure, union, or array. Zero for such
+references and for indirections through pointers, even pointers pointing
+to scalar types. If both this flag and MEM_STRUCT_P are clear, then we
+don't know whether this MEM is in a structure or not. Both flags should
+never be simultaneously set.
@findex MEM_ALIAS_SET
@item MEM_ALIAS_SET (@var{x})
@cindex @code{integrated}, in @code{insn}
@item RTX_INTEGRATED_P (@var{insn})
Nonzero in an insn if it resulted from an in-line function call.
-Stored in the @code{integrated} field and printed as @samp{/i}. This
-may be deleted; nothing currently depends on it.
+Stored in the @code{integrated} field and printed as @samp{/i}.
+
+@findex RTX_FRAME_RELATED_P
+@item RTX_FRAME_RELATED_P (@var{x})
+Nonzero in an insn or expression which is part of a function
+prologue and sets the stack pointer, sets the frame pointer, or saves a
+register. This flag is required for exception handling support
+on targets with RTL prologues.
@findex SYMBOL_REF_USED
@cindex @code{used}, in @code{symbol_ref}
uses.
@end table
-@node Machine Modes, Constants, Flags, RTL
+@node Machine Modes
@section Machine Modes
@cindex machine modes
less than or equal to @code{HOST_BITS_PER_INT}.
@findex GET_MODE_ALIGNMENT
-@item GET_MODE_ALIGNMENT (@var{m)})
+@item GET_MODE_ALIGNMENT (@var{m})
Return the required alignment, in bits, for an object of mode @var{m}.
@findex GET_MODE_UNIT_SIZE
@code{BITS_PER_UNIT} or @code{BITS_PER_WORD}, respectively. On 32-bit
machines, these are @code{QImode} and @code{SImode}, respectively.
-@node Constants, Regs and Memory, Machine Modes, RTL
+@node Constants
@section Constant Expression Types
@cindex RTL constants
@cindex RTL constant expression types
@var{m} should be @code{Pmode}.
@end table
-@node Regs and Memory, Arithmetic, Constants, RTL
+@node Regs and Memory
@section Registers and Memory
@cindex RTL register expressions
@cindex RTL memory expressions
by incrementing it, but there is no need to mention this in the RTL.
@findex mem
-@item (mem:@var{m} @var{addr})
+@item (mem:@var{m} @var{addr} @var{alias})
This RTX represents a reference to main memory at an address
represented by the expression @var{addr}. @var{m} specifies how large
-a unit of memory is accessed.
+a unit of memory is accessed. @var{alias} specifies an alias set for the
+reference. In general two items are in different alias sets if they cannot
+reference the same memory address.
@findex addressof
@item (addressof:@var{m} @var{reg})
expression for the address of its stack slot.
@end table
-@node Arithmetic, Comparisons, Regs and Memory, RTL
+@node Arithmetic
@section RTL Expressions for Arithmetic
@cindex arithmetic, in RTL
@cindex math, in RTL
@item (minus:@var{m} @var{x} @var{y})
Like @code{plus} but represents subtraction.
+@findex ss_plus
+@cindex RTL addition with signed saturation
+@item (ss_plus:@var{m} @var{x} @var{y})
+
+Like @code{plus}, but using signed saturation in case of an overflow.
+
+@findex us_plus
+@cindex RTL addition with unsigned saturation
+@item (us_plus:@var{m} @var{x} @var{y})
+
+Like @code{plus}, but using unsigned saturation in case of an overflow.
+
+@findex ss_minus
+@cindex RTL addition with signed saturation
+@item (ss_minus:@var{m} @var{x} @var{y})
+
+Like @code{minus}, but using signed saturation in case of an overflow.
+
+@findex us_minus
+@cindex RTL addition with unsigned saturation
+@item (us_minus:@var{m} @var{x} @var{y})
+
+Like @code{minus}, but using unsigned saturation in case of an overflow.
+
@findex compare
@cindex RTL comparison
@item (compare:@var{m} @var{x} @var{y})
valid.
@end table
-@node Comparisons, Bit Fields, Arithmetic, RTL
+@node Comparisons
@section Comparison Operations
@cindex RTL comparison operations
comparison operators may be used to compare the condition codes
@code{(cc0)} against zero, as in @code{(eq (cc0) (const_int 0))}. Such
a construct actually refers to the result of the preceding instruction
-in which the condition codes were set. The instructing setting the
+in which the condition codes were set. The instruction setting the
condition code must be adjacent to the instruction using the condition
code; only @code{note} insns may separate them.
for insn attributes. @xref{Insn Attributes}.
@end table
-@node Bit Fields, Conversions, Comparisons, RTL
+@node Bit Fields
@section Bit Fields
@cindex bit fields
are filled to an entire word with zeros instead of by sign-extension.
@end table
-@node Conversions, RTL Declarations, Bit Fields, RTL
+@node Vector Operations
+@section Vector Operations
+@cindex vector operations
+
+All normal rtl expressions can be used with vector modes; they are
+interpreted as operating on each part of the vector independently.
+Additionally, there are a few new expressions to describe specific vector
+operations.
+
+@table @code
+@findex vec_merge
+@item (vec_merge:@var{m} @var{vec1} @var{vec2} @var{items})
+This describes a merge operation between two vectors. The result is a vector
+of mode @var{m}; its elements are selected from either @var{vec1} or
+@var{vec2}. Which elements are selected is described by @var{items}, which
+is a bit mask represented by a @code{const_int}; a zero bit indicates the
+corresponding element in the result vector is taken from @var{vec2} while
+a set bit indicates it is taken from @var{vec1}.
+
+@findex vec_select
+@item (vec_select:@var{m} @var{vec1} @var{selection})
+This describes an operation that selects parts of a vector. @var{vec1} is
+the source vector, @var{selection} is a @code{parallel} that contains a
+@code{const_int} for each of the subparts of the result vector, giving the
+number of the source subpart that should be stored into it.
+
+@findex vec_concat
+@item (vec_concat:@var{m} @var{vec1} @var{vec2})
+Describes a vector concat operation. The result is a concatenation of the
+vectors @var{vec1} and @var{vec2}; its length is the sum of the lengths of
+the two inputs.
+
+@findex vec_const
+@item (vec_const:@var{m} @var{subparts})
+This describes a constant vector. @var{subparts} is a @code{parallel} that
+contains a constant for each of the subparts of the vector.
+
+@findex vec_duplicate
+@item (vec_duplicate:@var{m} @var{vec})
+This operation converts a small vector into a larger one by duplicating the
+input values. The output vector mode must have the same submodes as the
+input vector mode, and the number of output parts must be an integer multiple
+of the number of input parts.
+
+@end table
+
+@node Conversions
@section Conversions
@cindex conversions
@cindex machine mode conversions
to machine mode @var{m}. @var{m} must be a fixed-point mode
and @var{x} a fixed-point value of a mode wider than @var{m}.
+@findex ss_truncate
+@item (ss_truncate:@var{m} @var{x})
+Represents the result of truncating the value @var{x}
+to machine mode @var{m}, using signed saturation in the case of
+overflow. Both @var{m} and the mode of @var{x} must be fixed-point
+modes.
+
+@findex us_truncate
+@item (us_truncate:@var{m} @var{x})
+Represents the result of truncating the value @var{x}
+to machine mode @var{m}, using unsigned saturation in the case of
+overflow. Both @var{m} and the mode of @var{x} must be fixed-point
+modes.
+
@findex float_truncate
@item (float_truncate:@var{m} @var{x})
Represents the result of truncating the value @var{x}
towards zero.
@end table
-@node RTL Declarations, Side Effects, Conversions, RTL
+@node RTL Declarations
@section Declarations
@cindex RTL declarations
@cindex declarations, RTL
register when @var{m} is less than a word.
@end table
-@node Side Effects, Incdec, RTL Declarations, RTL
+@node Side Effects
@section Side Effect Expressions
@cindex RTL side effect expressions
and of @var{min} and @var{max} to @var{base}. See rtl.def for details.@refill
@end table
-@node Incdec, Assembler, Side Effects, RTL
+@node Incdec
@section Embedded Side-Effects on Addresses
@cindex RTL preincrement
@cindex RTL postincrement
@cindex RTL predecrement
@cindex RTL postdecrement
-Four special side-effect expression codes appear as memory addresses.
+Six special side-effect expression codes appear as memory addresses.
@table @code
@findex pre_dec
@findex post_inc
@item (post_inc:@var{m} @var{x})
Similar, but specifies incrementing @var{x} instead of decrementing it.
+
+@findex post_modify
+@item (post_modify:@var{m} @var{x} @var{y})
+
+Represents the side effect of setting @var{x} to @var{y} and
+represents @var{x} before @var{x} is modified. @var{x} must be a
+@code{reg} or @code{mem}, but most machines allow only a @code{reg}.
+@var{m} must be the machine mode for pointers on the machine in use.
+The amount @var{x} is decremented by is the length in bytes of the
+machine mode of the containing memory reference of which this expression
+serves as the address. Note that this is not currently implemented.
+
+The expression @var{y} must be one of three forms:
+@table @code
+@code{(plus:@var{m} @var{x} @var{z})},
+@code{(minus:@var{m} @var{x} @var{z})}, or
+@code{(plus:@var{m} @var{x} @var{i})},
+@end table
+where @var{z} is an index register and @var{i} is a constant.
+
+Here is an example of its use:@refill
+
+@example
+(mem:SF (post_modify:SI (reg:SI 42) (plus (reg:SI 42) (reg:SI 48))))
+@end example
+
+This says to modify pseudo register 42 by adding the contents of pseudo
+register 48 to it, after the use of what ever 42 points to.
+
+@findex post_modify
+@item (pre_modify:@var{m} @var{x} @var{expr})
+Similar except side effects happen before the use.
@end table
These embedded side effect expressions must be used with care. Instruction
additional parallel stores would require doubling the number of entries
in the machine description.
-@node Assembler, Insns, Incdec, RTL
+@node Assembler
@section Assembler Instructions as Expressions
@cindex assembler instructions in RTL
output operand. They are also distinguished by the output-operand index
number, which is 0, 1, @dots{} for successive output operands.
-@node Insns, Calls, Assembler, RTL
+@node Insns
@section Insns
@cindex insns
phase is completed and contains the number of times this label is
referenced in the current function.
+@findex LABEL_ALTERNATE_NAME
+The field @code{LABEL_ALTERNATE_NAME} is used to associate a name with
+a @code{code_label}. If this field is defined, the alternate name will
+be emitted instead of an internally generated label name.
+
@findex barrier
@item barrier
Barriers are placed in the instruction stream when control cannot flow
These codes are printed symbolically when they appear in debugging dumps.
@end table
+@cindex @code{TImode}, in @code{insn}
@cindex @code{HImode}, in @code{insn}
@cindex @code{QImode}, in @code{insn}
The machine mode of an insn is normally @code{VOIDmode}, but some
-phases use the mode for various purposes; for example, the reload pass
-sets it to @code{HImode} if the insn needs reloading but not register
-elimination and @code{QImode} if both are required. The common
-subexpression elimination pass sets the mode of an insn to @code{QImode}
-when it is the first insn in a block that has already been processed.
+phases use the mode for various purposes.
+
+The common subexpression elimination pass sets the mode of an insn to
+@code{QImode} when it is the first insn in a block that has already
+been processed.
+
+The second Haifa scheduling pass, for targets that can multiple issue,
+sets the mode of an insn to @code{TImode} when it is believed that the
+instruction begins an issue group. That is, when the instruction
+cannot issue simultaneously with the previous. This may be relied on
+by later passes, in particular machine-dependant reorg.
Here is a table of the extra fields of @code{insn}, @code{jump_insn}
and @code{call_insn} insns:
A @code{REG_EQUAL} note will also usually be attached to this insn to
provide the expression being computed by the sequence.
+These notes will be deleted after reload, since they are no longer
+accurate or useful.
+
@findex REG_LIBCALL
@item REG_LIBCALL
This is the inverse of @code{REG_RETVAL}: it is placed on the first
insn of a multi-insn sequence, and it points to the last one.
+These notes are deleted after reload, since they are no longer useful or
+accurate.
+
@findex REG_CC_SETTER
@findex REG_CC_USER
@item REG_CC_SETTER
These notes are found in JUMP insns after delayed branch scheduling
has taken place. They indicate both the direction and the likelyhood
of the JUMP. The format is a bitmask of ATTR_FLAG_* values.
+
+@findex REG_FRAME_RELATED_EXPR
+@item REG_FRAME_RELATED_EXPR
+This is used on an RTX_FRAME_RELATED_P insn wherein the attached expression
+is used in place of the actual insn pattern. This is done in cases where
+the pattern is either complex or misleading.
@end table
For convenience, the machine mode in an @code{insn_list} or
unique id; the first operand of an @code{expr_list} is printed in the
ordinary way as an expression.
-@node Calls, Sharing, Insns, RTL
+@node Calls
@section RTL Representation of Function-Call Insns
@cindex calling functions in RTL
@cindex RTL function-call insns
@cindex @code{const_int}, RTL sharing
@item
-There is only one @code{const_int} expression with value 0, only
-one with value 1, and only one with value @minus{}1.
-Some other integer values are also stored uniquely.
+All @code{const_int} expressions with equal values are shared.
@cindex @code{pc}, RTL sharing
@item
OSDN Git Service
