/* This file contains the definitions and documentation for the
Register Transfer Expressions (rtx's) that make up the
Register Transfer Language (rtl) used in the Back End of the GNU compiler.
- Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999
+ Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
Free Software Foundation, Inc.
This file is part of GNU CC.
"i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
"m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
"g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
+ "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
"x" everything else
*/
(`operands' is an alias here for `recog_operand'). */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
+/* Definition of an insn and associated split.
+ This is the concatenation, with a few modifications, of a define_insn
+ and a define_split which share the same pattern.
+ Operand:
+ 0: names this instruction.
+ If the name is the null string, the instruction is in the
+ machine description just to be recognized, and will never be emitted by
+ the tree to rtl expander.
+ 1: is the pattern.
+ 2: is a string which is a C expression
+ giving an additional condition for recognizing this pattern.
+ A null string means no extra condition.
+ 3: is the action to execute if this pattern is matched.
+ If this assembler code template starts with a * then it is a fragment of
+ C code to run to decide on a template to use. Otherwise, it is the
+ template to use.
+ 4: C expression that must be true for split. This may start with "&&"
+ in which case the split condition is the logical and of the insn
+ condition and what follows the "&&" of this operand.
+ 5: vector of insn patterns to place into a SEQUENCE
+ 6: optionally, some C code to execute before generating the
+ insns. This might, for example, create some RTX's and store them in
+ elements of `recog_operand' for use by the vector of insn-patterns.
+ (`operands' is an alias here for `recog_operand').
+ 7: optionally, a vector of attributes for this insn. */
+DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsssESV", 'x')
+
/* Definition of an RTL peephole operation.
Follows the same arguments as define_split. */
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
/* Define attribute computation for `asm' instructions. */
DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
+/* Definition of a conditional execution meta operation. Automatically
+ generates new instances of DEFINE_INSN, selected by having attribute
+ "predicable" true. The new pattern will contain a COND_EXEC and the
+ predicate at top-level.
+
+ Operand:
+ 0: The predicate pattern. The top-level form should match a
+ relational operator. Operands should have only one alternative.
+ 1: A C expression giving an additional condition for recognizing
+ the generated pattern.
+ 2: A template or C code to produce assembler output. */
+DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
+
/* SEQUENCE appears in the result of a `gen_...' function
for a DEFINE_EXPAND that wants to make several insns.
Its elements are the bodies of the insns that should be made.
`emit_insn' takes the SEQUENCE apart and makes separate insns. */
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
-/* Refers to the address of its argument.
- This appears only in machine descriptions, indicating that
- any expression that would be acceptable as the operand of MEM
- should be matched. */
+/* Refers to the address of its argument. This is only used in alias.c. */
DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
/* ----------------------------------------------------------------------
/* Holds a label that is followed by instructions.
Operand:
- 3: is a number that is unique in the entire compilation.
- 4: is the user-given name of the label, if any.
- 5: is used in jump.c for the use-count of the label.
- 6: is used in flow.c to point to the chain of label_ref's to this label. */
-DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00", 'x')
+ 3: is used in jump.c for the use-count of the label.
+ 4: is used in flow.c to point to the chain of label_ref's to this label.
+ 5: is a number that is unique in the entire compilation.
+ 6: is the user-given name of the label, if any.
+ 7: is the alternate label name. */
+DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuu00iss", 'x')
/* Say where in the code a source line starts, for symbol table's sake.
- Contains a filename and a line number. Line numbers <= 0 are special:
- 0 is used in a dummy placed at the front of every function
- just so there will never be a need to delete the first insn;
- -1 indicates a dummy; insns to be deleted by flow analysis and combining
- are really changed to NOTEs with a number of -1.
- -2 means beginning of a name binding contour; output N_LBRAC.
- -3 means end of a contour; output N_RBRAC. */
-DEF_RTL_EXPR(NOTE, "note", "iuu0n", 'x')
+ Operand:
+ 3: filename, if line number > 0, note-specific data otherwise.
+ 4: line number if > 0, enum note_insn otherwise.
+ 5: unique number if line number == note_insn_deleted_label. */
+DEF_RTL_EXPR(NOTE, "note", "iuu0ni", 'x')
/* ----------------------------------------------------------------------
Top level constituents of INSN, JUMP_INSN and CALL_INSN.
---------------------------------------------------------------------- */
-/* Several operations to be done in parallel. */
+/* Conditionally execute code.
+ Operand 0 is the condition that if true, the code is executed.
+ Operand 1 is the code to be executed (typically a SET).
+
+ Semantics are that there are no side effects if the condition
+ is false. This pattern is created automatically by the if_convert
+ pass run after reload or by target-specific splitters. */
+DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
+
+/* Several operations to be done in parallel (perhaps under COND_EXEC). */
DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
/* A string that is passed through to the assembler as input.
For an unconditional trap, make the condition (const_int 1). */
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
+/* Placeholder for _Unwind_Resume before we know if a function call
+ or a branch is needed. Operand 1 is the exception region from
+ which control is flowing. */
+DEF_RTL_EXPR(RESX, "resx", "i", 'x')
+
/* ----------------------------------------------------------------------
Primitive values for use in expressions.
---------------------------------------------------------------------- */
by a SET whose first operand is (PC). */
DEF_RTL_EXPR(PC, "pc", "", 'o')
+/* Used in the cselib routines to describe a value. */
+DEF_RTL_EXPR(VALUE, "value", "0", 'o')
+
/* A register. The "operand" is the register number, accessed with
the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
than a hardware register is being referred to. The second operand
- doesn't really exist. Unfortunately, however, the compiler
- implicitly assumes that a REG can be transformed in place into a
- MEM, and therefore that a REG is at least as big as a MEM. To
- avoid this memory overhead, which is likely to be substantial,
- search for uses of PUT_CODE that turn REGs into MEMs, and fix them
- somehow. Then, the trailing `0' can be removed here. */
+ holds the original register number - this will be different for a
+ pseudo register that got turned into a hard register.
+ This rtx needs to have as many (or more) fields as a MEM, since we
+ can change REG rtx's into MEMs during reload. */
DEF_RTL_EXPR(REG, "reg", "i0", 'o')
/* A scratch register. This represents a register used only within a
/* A memory location; operand is the address. Can be nested inside a
VOLATILE. The second operand is the alias set to which this MEM
- belongs. We use `0' instead of `i' for this field so that the
+ belongs. We use `0' instead of `w' for this field so that the
field need not be specified in machine descriptions. */
DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
/* Operand:
0: value to be shifted.
1: number of bits. */
-DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
-DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
-
-/* Right shift operations, for machines where these are not the same
- as left shifting with a negative argument. */
-
-DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
-DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
-DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
+DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
+DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
+DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
+DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
+DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
/* Minimum and maximum values of two operands. We need both signed and
unsigned forms. (We cannot use MIN for SMIN because it conflicts
containing MEM. These operations exist in only two cases:
1. pushes onto the stack.
2. created automatically by the life_analysis pass in flow.c. */
-DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
-DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
-DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
-DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
+DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
+DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
+DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
+DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
/* These binary operations are used to represent generic address
side-effects in memory addresses, except for simple incrementation
or decrementation which use the above operations. They are
- created automatically by the life_analysis pass in flow.c.
- (Note that these operators are currently placeholders.) */
-DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'x')
-DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'x')
+ created automatically by the life_analysis pass in flow.c.
+ The first operand is a REG which is used as the address.
+ The second operand is an expression that is assigned to the
+ register, either before (PRE_MODIFY) or after (POST_MODIFY)
+ evaluating the address.
+ Currently, the compiler can only handle second operands of the
+ form (plus (reg) (reg)) and (plus (reg) (const_int)), where
+ the first operand of the PLUS has to be the same register as
+ the first operand of the *_MODIFY. */
+DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
+DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
/* Comparison operations. The ordered comparisons exist in two
flavors, signed and unsigned. */
DEF_RTL_EXPR(LEU, "leu", "ee", '<')
DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
+/* Additional floating point unordered comparision flavors. */
+DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
+DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
+
+/* These are equivalent to unordered or ... */
+DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
+DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
+DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
+DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
+DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
+
+/* This is an ordered NE, ie !UNEQ, ie false for NaN. */
+DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
+
/* Represents the result of sign-extending the sole operand.
The machine modes of the operand and of the SIGN_EXTEND expression
determine how much sign-extension is going on. */
of a constant expression. */
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
-/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_START insn.
+/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
the registers that can be substituted within this range. Operand 3 is the
number of calls in the range. Operand 4 is the number of insns in the
potential tail recursive calls were found.
The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
- after we select a call method. */
+ after we select a call method.
+
+ This method of tail-call elimination is intended to be replaced by
+ tree-based optimizations once front-end conversions are complete. */
DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
+/* Describes a merge operation between two vector values.
+ Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
+ that specifies where the parts of the result are taken from. Set bits
+ indicate operand 0, clear bits indicate operand 1. The parts are defined
+ by the mode of the vectors. */
+DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')
+
+/* Describes an operation that selects parts of a vector.
+ Operands 0 is the source vector, operand 1 is a PARALLEL that contains
+ a CONST_INT for each of the subparts of the result vector, giving the
+ number of the source subpart that should be stored into it. */
+DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')
+
+/* Describes a vector concat operation. Operands 0 and 1 are the source
+ vectors, the result is a vector that is as long as operands 0 and 1
+ combined and is the concatenation of the two source vectors. */
+DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')
+
+/* Describes a vector constant. Each part of the PARALLEL that is operand 0
+ describes a constant for one of the subparts. */
+DEF_RTL_EXPR(VEC_CONST, "vec_const", "e", 'x')
+
+/* Describes an operation that converts a small vector into a larger one by
+ duplicating the input values. The output vector mode must have the same
+ submodes as the input vector mode, and the number of output parts must be
+ an integer multiple of the number of input parts. */
+DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
+
+/* Addition with signed saturation */
+DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
+
+/* Addition with unsigned saturation */
+DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
+
+/* Operand 0 minus operand 1, with signed saturation. */
+DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
+
+/* Operand 0 minus operand 1, with unsigned saturation. */
+DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
+
+/* Signed saturating truncate. */
+DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
+
+/* Unsigned saturating truncate. */
+DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
+
+/* The SSA phi operator.
+
+ The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
+ containing the block number of the predecessor through which control
+ has passed when the register at element 2N is used.
+
+ Note that PHI may only appear at the beginning of a basic block.
+
+ ??? There may be multiple PHI insns, but they are all evaluated
+ in parallel. This probably ought to be changed to use a real
+ PARALLEL, as that would be less confusing and more in the spirit
+ of canonical RTL. It is, however, easier to manipulate this way. */
+DEF_RTL_EXPR(PHI, "phi", "E", 'x')
+
+
/*
Local variables:
mode:c
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