Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
Free Software Foundation, Inc.
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+along with GCC; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
/* Expression definitions and descriptions for all targets are in this file.
"i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
"m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
"g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
+ "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
"x" everything else
*/
DEF_RTL_EXPR(NIL, "nil", "*", 'x')
+
+/* include a file */
+
+DEF_RTL_EXPR(INCLUDE, "include", "s", 'x')
+
/* ---------------------------------------------------------------------
Expressions used in constructing lists.
--------------------------------------------------------------------- */
template to use.
4: optionally, a vector of attributes for this insn.
*/
-DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
+DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x')
/* Definition of a peephole optimization.
1st operand: vector of insn patterns to match
3rd operand: template or C code to produce assembler output.
4: optionally, a vector of attributes for this insn.
*/
-DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
+DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x')
/* Definition of a split operation.
1st operand: insn pattern to match
3rd operand: vector of insn patterns to place into a SEQUENCE
4th operand: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
- elements of `recog_operand' for use by the vector of insn-patterns.
- (`operands' is an alias here for `recog_operand'). */
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
/* Definition of an insn and associated split.
5: vector of insn patterns to place into a SEQUENCE
6: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
- elements of `recog_operand' for use by the vector of insn-patterns.
- (`operands' is an alias here for `recog_operand').
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand').
7: optionally, a vector of attributes for this insn. */
-DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsssESV", 'x')
+DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x')
/* Definition of an RTL peephole operation.
Follows the same arguments as define_split. */
/* Define how to generate multiple insns for a standard insn name.
1st operand: the insn name.
2nd operand: vector of insn-patterns.
- Use match_operand to substitute an element of `recog_operand'.
+ Use match_operand to substitute an element of `recog_data.operand'.
3rd operand: C expression that must be true for this to be available.
This may not test any operands.
4th operand: Extra C code to execute before generating the insns.
This might, for example, create some RTX's and store them in
- elements of `recog_operand' for use by the vector of insn-patterns.
- (`operands' is an alias here for `recog_operand'). */
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
/* Define a requirement for delay slots.
DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
/* ----------------------------------------------------------------------
+ Constructions for CPU pipeline description described by NDFAs.
+ These do not appear in actual rtl code in the compiler.
+ ---------------------------------------------------------------------- */
+
+/* (define_cpu_unit string [string]) describes cpu functional
+ units (separated by comma).
+
+ 1st operand: Names of cpu functional units.
+ 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
+
+ All define_reservations, define_cpu_units, and
+ define_query_cpu_units should have unique names which may not be
+ "nothing". */
+DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x')
+
+/* (define_query_cpu_unit string [string]) describes cpu functional
+ units analogously to define_cpu_unit. If we use automaton without
+ minimization, the reservation of such units can be queried for
+ automaton state. */
+DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x')
+
+/* (exclusion_set string string) means that each CPU functional unit
+ in the first string can not be reserved simultaneously with any
+ unit whose name is in the second string and vise versa. CPU units
+ in the string are separated by commas. For example, it is useful
+ for description CPU with fully pipelined floating point functional
+ unit which can execute simultaneously only single floating point
+ insns or only double floating point insns. All CPU functional
+ units in a set should belong the same automaton. */
+DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x')
+
+/* (presence_set string string) means that each CPU functional unit in
+ the first string can not be reserved unless at least one of units
+ whose names are in the second string is reserved. This is an
+ asymmetric relation. CPU units in the string are separated by
+ commas. For example, it is useful for description that slot1 is
+ reserved after slot0 reservation for VLIW processor. All CPU
+ functional units in a set should belong the same automaton. */
+DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x')
+
+/* (absence_set string string) means that each CPU functional unit in
+ the first string can not be reserved only if each unit whose name
+ is in the second string is not reserved. This is an asymmetric
+ relation (actually exclusion set is analogous to this one but it is
+ symmetric). CPU units in the string are separated by commas. For
+ example, it is useful for description that slot0 can not be
+ reserved after slot1 or slot2 reservation for VLIW processor. All
+ CPU functional units in a set should belong the same automaton. */
+DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x')
+
+/* (define_bypass number out_insn_names in_insn_names) names bypass
+ with given latency (the first number) from insns given by the first
+ string (see define_insn_reservation) into insns given by the second
+ string. Insn names in the strings are separated by commas. The
+ third operand is optional name of function which is additional
+ guard for the bypass. The function will get the two insns as
+ parameters. If the function returns zero the bypass will be
+ ignored for this case. Additional guard is necessary to recognize
+ complicated bypasses, e.g. when consumer is load address. */
+DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x')
+
+/* (define_automaton string) describes names of automata generated and
+ used for pipeline hazards recognition. The names are separated by
+ comma. Actually it is possibly to generate the single automaton
+ but unfortunately it can be very large. If we use more one
+ automata, the summary size of the automata usually is less than the
+ single one. The automaton name is used in define_cpu_unit and
+ define_query_cpu_unit. All automata should have unique names. */
+DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x')
+
+/* (automata_option string) describes option for generation of
+ automata. Currently there are the following options:
+
+ o "no-minimization" which makes no minimization of automata. This
+ is only worth to do when we are going to query CPU functional
+ unit reservations in an automaton state.
+
+ o "w" which means generation of file describing the result
+ automaton. The file can be used for the description verification.
+
+ o "ndfa" which makes nondeterministic finite state automata. */
+DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x')
+
+/* (define_reservation string string) names reservation (the first
+ string) of cpu functional units (the 2nd string). Sometimes unit
+ reservations for different insns contain common parts. In such
+ case, you can describe common part and use its name (the 1st
+ parameter) in regular expression in define_insn_reservation. All
+ define_reservations, define_cpu_units, and define_query_cpu_units
+ should have unique names which may not be "nothing". */
+DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x')
+
+/* (define_insn_reservation name default_latency condition regexpr)
+ describes reservation of cpu functional units (the 3nd operand) for
+ instruction which is selected by the condition (the 2nd parameter).
+ The first parameter is used for output of debugging information.
+ The reservations are described by a regular expression according
+ the following syntax:
+
+ regexp = regexp "," oneof
+ | oneof
+
+ oneof = oneof "|" allof
+ | allof
+
+ allof = allof "+" repeat
+ | repeat
+
+ repeat = element "*" number
+ | element
+
+ element = cpu_function_unit_name
+ | reservation_name
+ | result_name
+ | "nothing"
+ | "(" regexp ")"
+
+ 1. "," is used for describing start of the next cycle in
+ reservation.
+
+ 2. "|" is used for describing the reservation described by the
+ first regular expression *or* the reservation described by the
+ second regular expression *or* etc.
+
+ 3. "+" is used for describing the reservation described by the
+ first regular expression *and* the reservation described by the
+ second regular expression *and* etc.
+
+ 4. "*" is used for convinience and simply means sequence in
+ which the regular expression are repeated NUMBER times with
+ cycle advancing (see ",").
+
+ 5. cpu functional unit name which means its reservation.
+
+ 6. reservation name -- see define_reservation.
+
+ 7. string "nothing" means no units reservation. */
+
+DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x')
+
+/* ----------------------------------------------------------------------
Expressions used for insn attributes. These also do not appear in
actual rtl code in the compiler.
---------------------------------------------------------------------- */
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
+/* Memory prefetch, with attributes supported on some targets.
+ Operand 1 is the address of the memory to fetch.
+ Operand 2 is 1 for a write access, 0 otherwise.
+ Operand 3 is the level of temporal locality; 0 means there is no
+ temporal locality and 1, 2, and 3 are for increasing levels of temporal
+ locality.
+
+ The attributes specified by operands 2 and 3 are ignored for targets
+ whose prefetch instructions do not support them. */
+DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x')
+
/* ----------------------------------------------------------------------
At the top level of an instruction (perhaps under PARALLEL).
---------------------------------------------------------------------- */
For an unconditional trap, make the condition (const_int 1). */
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
+/* Placeholder for _Unwind_Resume before we know if a function call
+ or a branch is needed. Operand 1 is the exception region from
+ which control is flowing. */
+DEF_RTL_EXPR(RESX, "resx", "i", 'x')
+
/* ----------------------------------------------------------------------
Primitive values for use in expressions.
---------------------------------------------------------------------- */
DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
/* numeric floating point constant.
- Operand 0 ('e') is the MEM that stores this constant in memory, or
- various other things (see comments at immed_double_const in
- varasm.c).
- Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the
+ Operand 0 ('0') is a chain of all CONST_DOUBLEs in use in the
current function.
Remaining operands hold the actual value. They are all 'w' and
there may be from 1 to 4; see rtl.c. */
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
+/* Describes a vector constant. */
+DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x')
+
/* String constant. Used only for attributes right now. */
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
/* A register. The "operand" is the register number, accessed with
the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
than a hardware register is being referred to. The second operand
- doesn't really exist. Unfortunately, however, the compiler
- implicitly assumes that a REG can be transformed in place into a
- MEM, and therefore that a REG is at least as big as a MEM. To
- avoid this memory overhead, which is likely to be substantial,
- search for uses of PUT_CODE that turn REGs into MEMs, and fix them
- somehow. Then, the trailing `0' can be removed here. */
+ holds the original register number - this will be different for a
+ pseudo register that got turned into a hard register.
+ This rtx needs to have as many (or more) fields as a MEM, since we
+ can change REG rtx's into MEMs during reload. */
DEF_RTL_EXPR(REG, "reg", "i0", 'o')
/* A scratch register. This represents a register used only within a
in DECL_RTLs and during RTL generation, but not in the insn chain. */
DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
-/* A memory location; operand is the address. Can be nested inside a
- VOLATILE. The second operand is the alias set to which this MEM
- belongs. We use `0' instead of `i' for this field so that the
- field need not be specified in machine descriptions. */
+/* A memory location; operand is the address. The second operand is the
+ alias set to which this MEM belongs. We use `0' instead of `w' for this
+ field so that the field need not be specified in machine descriptions. */
DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
/* Reference to an assembler label in the code for this function.
containing MEM. These operations exist in only two cases:
1. pushes onto the stack.
2. created automatically by the life_analysis pass in flow.c. */
-DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
-DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
-DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
-DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
+DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
+DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
+DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
+DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
/* These binary operations are used to represent generic address
side-effects in memory addresses, except for simple incrementation
or decrementation which use the above operations. They are
- created automatically by the life_analysis pass in flow.c.
- (Note that these operators are currently placeholders.) */
-DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'x')
-DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'x')
+ created automatically by the life_analysis pass in flow.c.
+ The first operand is a REG which is used as the address.
+ The second operand is an expression that is assigned to the
+ register, either before (PRE_MODIFY) or after (POST_MODIFY)
+ evaluating the address.
+ Currently, the compiler can only handle second operands of the
+ form (plus (reg) (reg)) and (plus (reg) (const_int)), where
+ the first operand of the PLUS has to be the same register as
+ the first operand of the *_MODIFY. */
+DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
+DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
/* Comparison operations. The ordered comparisons exist in two
flavors, signed and unsigned. */
tree-based optimizations once front-end conversions are complete. */
DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
+/* Describes a merge operation between two vector values.
+ Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
+ that specifies where the parts of the result are taken from. Set bits
+ indicate operand 0, clear bits indicate operand 1. The parts are defined
+ by the mode of the vectors. */
+DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')
+
+/* Describes an operation that selects parts of a vector.
+ Operands 0 is the source vector, operand 1 is a PARALLEL that contains
+ a CONST_INT for each of the subparts of the result vector, giving the
+ number of the source subpart that should be stored into it. */
+DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')
+
+/* Describes a vector concat operation. Operands 0 and 1 are the source
+ vectors, the result is a vector that is as long as operands 0 and 1
+ combined and is the concatenation of the two source vectors. */
+DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')
+
+/* Describes an operation that converts a small vector into a larger one by
+ duplicating the input values. The output vector mode must have the same
+ submodes as the input vector mode, and the number of output parts must be
+ an integer multiple of the number of input parts. */
+DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
+
+/* Addition with signed saturation */
+DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
+
+/* Addition with unsigned saturation */
+DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
+
+/* Operand 0 minus operand 1, with signed saturation. */
+DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
+
+/* Operand 0 minus operand 1, with unsigned saturation. */
+DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
+
+/* Signed saturating truncate. */
+DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
+
+/* Unsigned saturating truncate. */
+DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
+
/* The SSA phi operator.
The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT