DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x')
/* (define_query_cpu_unit string [string]) describes cpu functional
- units analogously to define_cpu_unit. If we use automaton without
- minimization, the reservation of such units can be queried for
- automaton state. */
+ units analogously to define_cpu_unit. The reservation of such
+ units can be queried for automaton state. */
DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x')
/* (exclusion_set string string) means that each CPU functional unit
for description CPU with fully pipelined floating point functional
unit which can execute simultaneously only single floating point
insns or only double floating point insns. All CPU functional
- units in a set should belong the same automaton. */
+ units in a set should belong to the same automaton. */
DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x')
/* (presence_set string string) means that each CPU functional unit in
- the first string can not be reserved unless at least one of units
- whose names are in the second string is reserved. This is an
- asymmetric relation. CPU units in the string are separated by
- commas. For example, it is useful for description that slot1 is
- reserved after slot0 reservation for VLIW processor. All CPU
- functional units in a set should belong the same automaton. */
+ the first string can not be reserved unless at least one of pattern
+ of units whose names are in the second string is reserved. This is
+ an asymmetric relation. CPU units or unit patterns in the strings
+ are separated by commas. Pattern is one unit name or unit names
+ separated by white-spaces.
+
+ For example, it is useful for description that slot1 is reserved
+ after slot0 reservation for a VLIW processor. We could describe it
+ by the following construction
+
+ (presence_set "slot1" "slot0")
+
+ Or slot1 is reserved only after slot0 and unit b0 reservation. In
+ this case we could write
+
+ (presence_set "slot1" "slot0 b0")
+
+ All CPU functional units in a set should belong to the same
+ automaton. */
DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x')
+/* (final_presence_set string string) is analogous to `presence_set'.
+ The difference between them is when checking is done. When an
+ instruction is issued in given automaton state reflecting all
+ current and planned unit reservations, the automaton state is
+ changed. The first state is a source state, the second one is a
+ result state. Checking for `presence_set' is done on the source
+ state reservation, checking for `final_presence_set' is done on the
+ result reservation. This construction is useful to describe a
+ reservation which is actually two subsequent reservations. For
+ example, if we use
+
+ (presence_set "slot1" "slot0")
+
+ the following insn will be never issued (because slot1 requires
+ slot0 which is absent in the source state).
+
+ (define_reservation "insn_and_nop" "slot0 + slot1")
+
+ but it can be issued if we use analogous `final_presence_set'. */
+DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", 'x')
+
/* (absence_set string string) means that each CPU functional unit in
- the first string can not be reserved only if each unit whose name
- is in the second string is not reserved. This is an asymmetric
- relation (actually exclusion set is analogous to this one but it is
- symmetric). CPU units in the string are separated by commas. For
- example, it is useful for description that slot0 can not be
- reserved after slot1 or slot2 reservation for VLIW processor. All
- CPU functional units in a set should belong the same automaton. */
+ the first string can be reserved only if each pattern of units
+ whose names are in the second string is not reserved. This is an
+ asymmetric relation (actually exclusion set is analogous to this
+ one but it is symmetric). CPU units or unit patterns in the string
+ are separated by commas. Pattern is one unit name or unit names
+ separated by white-spaces.
+
+ For example, it is useful for description that slot0 can not be
+ reserved after slot1 or slot2 reservation for a VLIW processor. We
+ could describe it by the following construction
+
+ (absence_set "slot2" "slot0, slot1")
+
+ Or slot2 can not be reserved if slot0 and unit b0 are reserved or
+ slot1 and unit b1 are reserved . In this case we could write
+
+ (absence_set "slot2" "slot0 b0, slot1 b1")
+
+ All CPU functional units in a set should to belong the same
+ automaton. */
DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x')
+/* (final_absence_set string string) is analogous to `absence_set' but
+ checking is done on the result (state) reservation. See comments
+ for `final_presence_set'. */
+DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", 'x')
+
/* (define_bypass number out_insn_names in_insn_names) names bypass
with given latency (the first number) from insns given by the first
string (see define_insn_reservation) into insns given by the second
automata. Currently there are the following options:
o "no-minimization" which makes no minimization of automata. This
- is only worth to do when we are going to query CPU functional
- unit reservations in an automaton state.
+ is only worth to do when we are debugging the description and
+ need to look more accurately at reservations of states.
o "time" which means printing additional time statistics about
generation of automata.
---------------------------------------------------------------------- */
/* An instruction that cannot jump. */
-DEF_RTL_EXPR(INSN, "insn", "iuuBteiee", 'i')
+DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", 'i')
/* An instruction that can possibly jump.
Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
-DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBteiee0", 'i')
+DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", 'i')
/* An instruction that can possibly call a subroutine
but which will not change which instruction comes next
in the current function.
Field ( rtx->fld[9] ) is CALL_INSN_FUNCTION_USAGE.
All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
-DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBteieee", 'i')
+DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", 'i')
/* A marker that indicates that control will not flow through. */
DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x')
DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
/* numeric floating point constant.
- Operand 0 ('0') is a chain of all CONST_DOUBLEs in use in the
- current function.
- Remaining operands hold the actual value. They are all 'w' and
- there may be from 1 to 4; see rtl.c. */
+ Operands hold the value. They are all 'w' and there may be from 2 to 6;
+ see real.h. */
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
/* Describes a vector constant. */
pseudo register that got turned into a hard register.
This rtx needs to have as many (or more) fields as a MEM, since we
can change REG rtx's into MEMs during reload. */
-DEF_RTL_EXPR(REG, "reg", "i0", 'o')
+DEF_RTL_EXPR(REG, "reg", "i00", 'o')
/* A scratch register. This represents a register used only within a
single insn. It will be turned into a REG during register allocation
LABEL_NEXTREF and CONTAINING_INSN. */
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
-/* Reference to a named label: the string that is the first operand,
- with `_' added implicitly in front.
- Exception: if the first character explicitly given is `*',
- to give it to the assembler, remove the `*' and do not add `_'. */
-DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
+/* Reference to a named label:
+ Operand 0: label name
+ Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
+ Operand 2: tree from which this symbol is derived, or null.
+ This is either a DECL node, or some kind of constant. */
+DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", 'o')
/* The condition code register is represented, in our imagination,
as a register holding a value that can be compared to zero.
DEF_RTL_EXPR(LEU, "leu", "ee", '<')
DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
-/* Additional floating point unordered comparision flavors. */
+/* Additional floating point unordered comparison flavors. */
DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
or 0 if arg is 0. */
DEF_RTL_EXPR(FFS, "ffs", "e", '1')
+/* Count leading zeros. */
+DEF_RTL_EXPR(CLZ, "clz", "e", '1')
+
+/* Count trailing zeros. */
+DEF_RTL_EXPR(CTZ, "ctz", "e", '1')
+
+/* Population count (number of 1 bits). */
+DEF_RTL_EXPR(POPCOUNT, "popcount", "e", '1')
+
+/* Population parity (number of 1 bits modulo 2). */
+DEF_RTL_EXPR(PARITY, "parity", "e", '1')
+
/* Reference to a signed bit-field of specified size and position.
Operand 0 is the memory unit (usually SImode or QImode) which
contains the field's first bit. Operand 1 is the width, in bits.
that specifies where the parts of the result are taken from. Set bits
indicate operand 0, clear bits indicate operand 1. The parts are defined
by the mode of the vectors. */
-DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')
+DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3')
/* Describes an operation that selects parts of a vector.
Operands 0 is the source vector, operand 1 is a PARALLEL that contains
a CONST_INT for each of the subparts of the result vector, giving the
number of the source subpart that should be stored into it. */
-DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')
+DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2')
/* Describes a vector concat operation. Operands 0 and 1 are the source
vectors, the result is a vector that is as long as operands 0 and 1
combined and is the concatenation of the two source vectors. */
-DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')
+DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2')
/* Describes an operation that converts a small vector into a larger one by
duplicating the input values. The output vector mode must have the same
submodes as the input vector mode, and the number of output parts must be
an integer multiple of the number of input parts. */
-DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
+DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1')
/* Addition with signed saturation */
DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
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