You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+02110-1301, USA. */
/* Instruction reorganization pass.
#include "resource.h"
#include "except.h"
#include "params.h"
+#include "timevar.h"
+#include "target.h"
+#include "tree-pass.h"
#ifdef DELAY_SLOTS
mostly_true_jump (rtx jump_insn, rtx condition)
{
rtx target_label = JUMP_LABEL (jump_insn);
- rtx insn, note;
- int rare_dest = rare_destination (target_label);
- int rare_fallthrough = rare_destination (NEXT_INSN (jump_insn));
+ rtx note;
+ int rare_dest, rare_fallthrough;
/* If branch probabilities are available, then use that number since it
always gives a correct answer. */
return -1;
}
- /* ??? Ought to use estimate_probability instead. */
-
- /* If this is a branch outside a loop, it is highly unlikely. */
- if (GET_CODE (PATTERN (jump_insn)) == SET
- && GET_CODE (SET_SRC (PATTERN (jump_insn))) == IF_THEN_ELSE
- && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 1)) == LABEL_REF
- && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 1)))
- || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 2)) == LABEL_REF
- && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 2)))))
- return -1;
-
- if (target_label)
- {
- /* If this is the test of a loop, it is very likely true. We scan
- backwards from the target label. If we find a NOTE_INSN_LOOP_BEG
- before the next real insn, we assume the branch is to the top of
- the loop. */
- for (insn = PREV_INSN (target_label);
- insn && NOTE_P (insn);
- insn = PREV_INSN (insn))
- if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
- return 2;
- }
-
/* Look at the relative rarities of the fallthrough and destination. If
they differ, we can predict the branch that way. */
+ rare_dest = rare_destination (target_label);
+ rare_fallthrough = rare_destination (NEXT_INSN (jump_insn));
switch (rare_fallthrough - rare_dest)
{
if (condition == 0)
return 0;
- /* EQ tests are usually false and NE tests are usually true. Also,
- most quantities are positive, so we can make the appropriate guesses
- about signed comparisons against zero. */
- switch (GET_CODE (condition))
- {
- case CONST_INT:
- /* Unconditional branch. */
- return 1;
- case EQ:
- return 0;
- case NE:
- return 1;
- case LE:
- case LT:
- if (XEXP (condition, 1) == const0_rtx)
- return 0;
- break;
- case GE:
- case GT:
- if (XEXP (condition, 1) == const0_rtx)
- return 1;
- break;
-
- default:
- break;
- }
-
/* Predict backward branches usually take, forward branches usually not. If
we don't know whether this is forward or backward, assume the branch
will be taken, since most are. */
if (! must_annul
&& ((condition == const_true_rtx
|| (! insn_sets_resource_p (trial, other_needed, 0)
- && ! may_trap_p (PATTERN (trial)))))
+ && ! may_trap_or_fault_p (PATTERN (trial)))))
? eligible_for_delay (insn, total_slots_filled, trial, flags)
: (must_annul || (delay_list == NULL && new_delay_list == NULL))
&& (must_annul = 1,
if (! must_annul
&& ((condition == const_true_rtx
|| (! insn_sets_resource_p (trial, other_needed, 0)
- && ! may_trap_p (PATTERN (trial)))))
+ && ! may_trap_or_fault_p (PATTERN (trial)))))
? eligible_for_delay (insn, *pslots_filled, trial, flags)
: (must_annul || delay_list == NULL) && (must_annul = 1,
check_annul_list_true_false (1, delay_list)
that reference values used in INSN. If we find one, then we move the
REG_DEAD note to INSN.
- This is needed to handle the case where an later insn (after INSN) has a
+ This is needed to handle the case where a later insn (after INSN) has a
REG_DEAD note for a register used by INSN, and this later insn subsequently
gets moved before a CODE_LABEL because it is a redundant insn. In this
case, mark_target_live_regs may be confused into thinking the register
}
}
\f
+/* Return the label before INSN, or put a new label there. */
+
+static rtx
+get_label_before (rtx insn)
+{
+ rtx label;
+
+ /* Find an existing label at this point
+ or make a new one if there is none. */
+ label = prev_nonnote_insn (insn);
+
+ if (label == 0 || !LABEL_P (label))
+ {
+ rtx prev = PREV_INSN (insn);
+
+ label = gen_label_rtx ();
+ emit_label_after (label, prev);
+ LABEL_NUSES (label) = 0;
+ }
+ return label;
+}
+
/* Scan a function looking for insns that need a delay slot and find insns to
put into the delay slot.
#ifdef HAVE_cc0
&& ! (reg_mentioned_p (cc0_rtx, pat) && ! sets_cc0_p (pat))
#endif
- && ! (maybe_never && may_trap_p (pat))
+ && ! (maybe_never && may_trap_or_fault_p (pat))
&& (trial = try_split (pat, trial, 0))
&& eligible_for_delay (insn, slots_filled, trial, flags)
&& ! can_throw_internal(trial))
#ifdef HAVE_cc0
&& ! reg_mentioned_p (cc0_rtx, PATTERN (next_trial))
#endif
- && ! (maybe_never && may_trap_p (PATTERN (next_trial)))
+ && ! (maybe_never && may_trap_or_fault_p (PATTERN (next_trial)))
&& (next_trial = try_split (PATTERN (next_trial), next_trial, 0))
&& eligible_for_delay (insn, slots_filled, next_trial, flags)
&& ! can_throw_internal (trial))
#endif
}
\f
+/* Follow any unconditional jump at LABEL;
+ return the ultimate label reached by any such chain of jumps.
+ Return null if the chain ultimately leads to a return instruction.
+ If LABEL is not followed by a jump, return LABEL.
+ If the chain loops or we can't find end, return LABEL,
+ since that tells caller to avoid changing the insn. */
+
+static rtx
+follow_jumps (rtx label)
+{
+ rtx insn;
+ rtx next;
+ rtx value = label;
+ int depth;
+
+ for (depth = 0;
+ (depth < 10
+ && (insn = next_active_insn (value)) != 0
+ && JUMP_P (insn)
+ && ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn)
+ && onlyjump_p (insn))
+ || GET_CODE (PATTERN (insn)) == RETURN)
+ && (next = NEXT_INSN (insn))
+ && BARRIER_P (next));
+ depth++)
+ {
+ rtx tem;
+
+ /* If we have found a cycle, make the insn jump to itself. */
+ if (JUMP_LABEL (insn) == label)
+ return label;
+
+ tem = next_active_insn (JUMP_LABEL (insn));
+ if (tem && (GET_CODE (PATTERN (tem)) == ADDR_VEC
+ || GET_CODE (PATTERN (tem)) == ADDR_DIFF_VEC))
+ break;
+
+ value = JUMP_LABEL (insn);
+ }
+ if (depth == 10)
+ return label;
+ return value;
+}
+
/* Try to find insns to place in delay slots.
INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
if (!must_annul
&& (condition == const_true_rtx
|| (! insn_sets_resource_p (trial, &opposite_needed, 1)
- && ! may_trap_p (pat))))
+ && ! may_trap_or_fault_p (pat))))
{
old_trial = trial;
trial = try_split (pat, trial, 0);
dest = SET_DEST (pat), src = SET_SRC (pat);
if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
&& rtx_equal_p (XEXP (src, 0), dest)
+ && (!FLOAT_MODE_P (GET_MODE (src))
+ || flag_unsafe_math_optimizations)
&& ! reg_overlap_mentioned_p (dest, XEXP (src, 1))
&& ! side_effects_p (pat))
{
}
}
\f
+static void delete_computation (rtx insn);
+
+/* Recursively delete prior insns that compute the value (used only by INSN
+ which the caller is deleting) stored in the register mentioned by NOTE
+ which is a REG_DEAD note associated with INSN. */
+
+static void
+delete_prior_computation (rtx note, rtx insn)
+{
+ rtx our_prev;
+ rtx reg = XEXP (note, 0);
+
+ for (our_prev = prev_nonnote_insn (insn);
+ our_prev && (NONJUMP_INSN_P (our_prev)
+ || CALL_P (our_prev));
+ our_prev = prev_nonnote_insn (our_prev))
+ {
+ rtx pat = PATTERN (our_prev);
+
+ /* If we reach a CALL which is not calling a const function
+ or the callee pops the arguments, then give up. */
+ if (CALL_P (our_prev)
+ && (! CONST_OR_PURE_CALL_P (our_prev)
+ || GET_CODE (pat) != SET || GET_CODE (SET_SRC (pat)) != CALL))
+ break;
+
+ /* If we reach a SEQUENCE, it is too complex to try to
+ do anything with it, so give up. We can be run during
+ and after reorg, so SEQUENCE rtl can legitimately show
+ up here. */
+ if (GET_CODE (pat) == SEQUENCE)
+ break;
+
+ if (GET_CODE (pat) == USE
+ && NONJUMP_INSN_P (XEXP (pat, 0)))
+ /* reorg creates USEs that look like this. We leave them
+ alone because reorg needs them for its own purposes. */
+ break;
+
+ if (reg_set_p (reg, pat))
+ {
+ if (side_effects_p (pat) && !CALL_P (our_prev))
+ break;
+
+ if (GET_CODE (pat) == PARALLEL)
+ {
+ /* If we find a SET of something else, we can't
+ delete the insn. */
+
+ int i;
+
+ for (i = 0; i < XVECLEN (pat, 0); i++)
+ {
+ rtx part = XVECEXP (pat, 0, i);
+
+ if (GET_CODE (part) == SET
+ && SET_DEST (part) != reg)
+ break;
+ }
+
+ if (i == XVECLEN (pat, 0))
+ delete_computation (our_prev);
+ }
+ else if (GET_CODE (pat) == SET
+ && REG_P (SET_DEST (pat)))
+ {
+ int dest_regno = REGNO (SET_DEST (pat));
+ int dest_endregno
+ = (dest_regno
+ + (dest_regno < FIRST_PSEUDO_REGISTER
+ ? hard_regno_nregs[dest_regno]
+ [GET_MODE (SET_DEST (pat))] : 1));
+ int regno = REGNO (reg);
+ int endregno
+ = (regno
+ + (regno < FIRST_PSEUDO_REGISTER
+ ? hard_regno_nregs[regno][GET_MODE (reg)] : 1));
+
+ if (dest_regno >= regno
+ && dest_endregno <= endregno)
+ delete_computation (our_prev);
+
+ /* We may have a multi-word hard register and some, but not
+ all, of the words of the register are needed in subsequent
+ insns. Write REG_UNUSED notes for those parts that were not
+ needed. */
+ else if (dest_regno <= regno
+ && dest_endregno >= endregno)
+ {
+ int i;
+
+ REG_NOTES (our_prev)
+ = gen_rtx_EXPR_LIST (REG_UNUSED, reg,
+ REG_NOTES (our_prev));
+
+ for (i = dest_regno; i < dest_endregno; i++)
+ if (! find_regno_note (our_prev, REG_UNUSED, i))
+ break;
+
+ if (i == dest_endregno)
+ delete_computation (our_prev);
+ }
+ }
+
+ break;
+ }
+
+ /* If PAT references the register that dies here, it is an
+ additional use. Hence any prior SET isn't dead. However, this
+ insn becomes the new place for the REG_DEAD note. */
+ if (reg_overlap_mentioned_p (reg, pat))
+ {
+ XEXP (note, 1) = REG_NOTES (our_prev);
+ REG_NOTES (our_prev) = note;
+ break;
+ }
+ }
+}
+
+/* Delete INSN and recursively delete insns that compute values used only
+ by INSN. This uses the REG_DEAD notes computed during flow analysis.
+ If we are running before flow.c, we need do nothing since flow.c will
+ delete dead code. We also can't know if the registers being used are
+ dead or not at this point.
+
+ Otherwise, look at all our REG_DEAD notes. If a previous insn does
+ nothing other than set a register that dies in this insn, we can delete
+ that insn as well.
+
+ On machines with CC0, if CC0 is used in this insn, we may be able to
+ delete the insn that set it. */
+
+static void
+delete_computation (rtx insn)
+{
+ rtx note, next;
+
+#ifdef HAVE_cc0
+ if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
+ {
+ rtx prev = prev_nonnote_insn (insn);
+ /* We assume that at this stage
+ CC's are always set explicitly
+ and always immediately before the jump that
+ will use them. So if the previous insn
+ exists to set the CC's, delete it
+ (unless it performs auto-increments, etc.). */
+ if (prev && NONJUMP_INSN_P (prev)
+ && sets_cc0_p (PATTERN (prev)))
+ {
+ if (sets_cc0_p (PATTERN (prev)) > 0
+ && ! side_effects_p (PATTERN (prev)))
+ delete_computation (prev);
+ else
+ /* Otherwise, show that cc0 won't be used. */
+ REG_NOTES (prev) = gen_rtx_EXPR_LIST (REG_UNUSED,
+ cc0_rtx, REG_NOTES (prev));
+ }
+ }
+#endif
+
+ for (note = REG_NOTES (insn); note; note = next)
+ {
+ next = XEXP (note, 1);
+
+ if (REG_NOTE_KIND (note) != REG_DEAD
+ /* Verify that the REG_NOTE is legitimate. */
+ || !REG_P (XEXP (note, 0)))
+ continue;
+
+ delete_prior_computation (note, insn);
+ }
+
+ delete_related_insns (insn);
+}
+
+/* If all INSN does is set the pc, delete it,
+ and delete the insn that set the condition codes for it
+ if that's what the previous thing was. */
+
+static void
+delete_jump (rtx insn)
+{
+ rtx set = single_set (insn);
+
+ if (set && GET_CODE (SET_DEST (set)) == PC)
+ delete_computation (insn);
+}
+
+\f
/* Once we have tried two ways to fill a delay slot, make a pass over the
code to try to improve the results and to do such things as more jump
threading. */
if (target_label && target_label != JUMP_LABEL (insn))
reorg_redirect_jump (insn, target_label);
- /* See if this jump branches around an unconditional jump.
- If so, invert this jump and point it to the target of the
+ /* See if this jump conditionally branches around an unconditional
+ jump. If so, invert this jump and point it to the target of the
second jump. */
if (next && JUMP_P (next)
+ && any_condjump_p (insn)
&& (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
&& target_label
&& next_active_insn (target_label) == next_active_insn (next)
if (JUMP_P (insn)
&& (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
&& (other = prev_active_insn (insn)) != 0
- && (condjump_p (other) || condjump_in_parallel_p (other))
+ && any_condjump_p (other)
&& no_labels_between_p (other, insn)
&& 0 > mostly_true_jump (other,
get_branch_condition (other,
continue;
}
- /* See if this jump (with its delay slots) branches around another
- jump (without delay slots). If so, invert this jump and point
- it to the target of the second jump. We cannot do this for
- annulled jumps, though. Again, don't convert a jump to a RETURN
- here. */
+ /* See if this jump (with its delay slots) conditionally branches
+ around an unconditional jump (without delay slots). If so, invert
+ this jump and point it to the target of the second jump. We cannot
+ do this for annulled jumps, though. Again, don't convert a jump to
+ a RETURN here. */
if (! INSN_ANNULLED_BRANCH_P (delay_insn)
&& any_condjump_p (delay_insn)
&& next && JUMP_P (next)
/* Try to find insns to place in delay slots. */
void
-dbr_schedule (rtx first, FILE *file)
+dbr_schedule (rtx first)
{
rtx insn, next, epilogue_insn = 0;
int i;
/* If the current function has no insns other than the prologue and
epilogue, then do not try to fill any delay slots. */
- if (n_basic_blocks == 0)
+ if (n_basic_blocks == NUM_FIXED_BLOCKS)
return;
/* Find the highest INSN_UID and allocate and initialize our map from
/* It is not clear why the line below is needed, but it does seem to be. */
unfilled_firstobj = obstack_alloc (&unfilled_slots_obstack, 0);
- if (file)
+ if (dump_file)
{
int i, j, need_comma;
int total_delay_slots[MAX_DELAY_HISTOGRAM + 1];
reorg_pass_number < MAX_REORG_PASSES;
reorg_pass_number++)
{
- fprintf (file, ";; Reorg pass #%d:\n", reorg_pass_number + 1);
+ fprintf (dump_file, ";; Reorg pass #%d:\n", reorg_pass_number + 1);
for (i = 0; i < NUM_REORG_FUNCTIONS; i++)
{
need_comma = 0;
- fprintf (file, ";; Reorg function #%d\n", i);
+ fprintf (dump_file, ";; Reorg function #%d\n", i);
- fprintf (file, ";; %d insns needing delay slots\n;; ",
+ fprintf (dump_file, ";; %d insns needing delay slots\n;; ",
num_insns_needing_delays[i][reorg_pass_number]);
for (j = 0; j < MAX_DELAY_HISTOGRAM + 1; j++)
if (num_filled_delays[i][j][reorg_pass_number])
{
if (need_comma)
- fprintf (file, ", ");
+ fprintf (dump_file, ", ");
need_comma = 1;
- fprintf (file, "%d got %d delays",
+ fprintf (dump_file, "%d got %d delays",
num_filled_delays[i][j][reorg_pass_number], j);
}
- fprintf (file, "\n");
+ fprintf (dump_file, "\n");
}
}
memset (total_delay_slots, 0, sizeof total_delay_slots);
total_delay_slots[0]++;
}
}
- fprintf (file, ";; Reorg totals: ");
+ fprintf (dump_file, ";; Reorg totals: ");
need_comma = 0;
for (j = 0; j < MAX_DELAY_HISTOGRAM + 1; j++)
{
if (total_delay_slots[j])
{
if (need_comma)
- fprintf (file, ", ");
+ fprintf (dump_file, ", ");
need_comma = 1;
- fprintf (file, "%d got %d delays", total_delay_slots[j], j);
+ fprintf (dump_file, "%d got %d delays", total_delay_slots[j], j);
}
}
- fprintf (file, "\n");
+ fprintf (dump_file, "\n");
#if defined (ANNUL_IFTRUE_SLOTS) || defined (ANNUL_IFFALSE_SLOTS)
- fprintf (file, ";; Reorg annuls: ");
+ fprintf (dump_file, ";; Reorg annuls: ");
need_comma = 0;
for (j = 0; j < MAX_DELAY_HISTOGRAM + 1; j++)
{
if (total_annul_slots[j])
{
if (need_comma)
- fprintf (file, ", ");
+ fprintf (dump_file, ", ");
need_comma = 1;
- fprintf (file, "%d got %d delays", total_annul_slots[j], j);
+ fprintf (dump_file, "%d got %d delays", total_annul_slots[j], j);
}
}
- fprintf (file, "\n");
+ fprintf (dump_file, "\n");
#endif
- fprintf (file, "\n");
+ fprintf (dump_file, "\n");
}
/* For all JUMP insns, fill in branch prediction notes, so that during
#endif
}
#endif /* DELAY_SLOTS */
+\f
+static bool
+gate_handle_delay_slots (void)
+{
+#ifdef DELAY_SLOTS
+ return flag_delayed_branch;
+#else
+ return 0;
+#endif
+}
+
+/* Run delay slot optimization. */
+static unsigned int
+rest_of_handle_delay_slots (void)
+{
+#ifdef DELAY_SLOTS
+ dbr_schedule (get_insns ());
+#endif
+ return 0;
+}
+
+struct tree_opt_pass pass_delay_slots =
+{
+ "dbr", /* name */
+ gate_handle_delay_slots, /* gate */
+ rest_of_handle_delay_slots, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_DBR_SCHED, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ TODO_dump_func |
+ TODO_ggc_collect, /* todo_flags_finish */
+ 'd' /* letter */
+};
+
+/* Machine dependent reorg pass. */
+static bool
+gate_handle_machine_reorg (void)
+{
+ return targetm.machine_dependent_reorg != 0;
+}
+
+
+static unsigned int
+rest_of_handle_machine_reorg (void)
+{
+ targetm.machine_dependent_reorg ();
+ return 0;
+}
+
+struct tree_opt_pass pass_machine_reorg =
+{
+ "mach", /* name */
+ gate_handle_machine_reorg, /* gate */
+ rest_of_handle_machine_reorg, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_MACH_DEP, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ TODO_dump_func |
+ TODO_ggc_collect, /* todo_flags_finish */
+ 'M' /* letter */
+};
+