SECONDARY_RELOAD_CLASS (CLASS, MODE, X)
#endif
-extern int memory_move_cost (enum machine_mode, enum reg_class, bool);
-extern int memory_move_secondary_cost (enum machine_mode, enum reg_class,
- bool);
+extern int register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
+extern int memory_move_cost (enum machine_mode, reg_class_t, bool);
+extern int memory_move_secondary_cost (enum machine_mode, reg_class_t, bool);
/* Maximum number of reloads we can need. */
#define MAX_RELOADS (2 * MAX_RECOG_OPERANDS * (MAX_REGS_PER_ADDRESS + 1))
extern int n_reloads;
#endif
-extern GTY (()) VEC(rtx,gc) *reg_equiv_memory_loc_vec;
-extern rtx *reg_equiv_constant;
-extern rtx *reg_equiv_invariant;
-extern rtx *reg_equiv_memory_loc;
-extern rtx *reg_equiv_address;
-extern rtx *reg_equiv_mem;
-extern rtx *reg_equiv_alt_mem_list;
+/* Target-dependent globals. */
+struct target_reload {
+ /* Nonzero if indirect addressing is supported when the innermost MEM is
+ of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
+ which these are valid is the same as spill_indirect_levels, above. */
+ bool x_indirect_symref_ok;
+
+ /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
+ bool x_double_reg_address_ok;
+
+ /* Nonzero if indirect addressing is supported on the machine; this means
+ that spilling (REG n) does not require reloading it into a register in
+ order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
+ value indicates the level of indirect addressing supported, e.g., two
+ means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
+ a hard register. */
+ bool x_spill_indirect_levels;
+
+ /* True if caller-save has been reinitialized. */
+ bool x_caller_save_initialized_p;
+
+ /* Modes for each hard register that we can save. The smallest mode is wide
+ enough to save the entire contents of the register. When saving the
+ register because it is live we first try to save in multi-register modes.
+ If that is not possible the save is done one register at a time. */
+ enum machine_mode (x_regno_save_mode
+ [FIRST_PSEUDO_REGISTER]
+ [MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]);
+
+ /* We will only make a register eligible for caller-save if it can be
+ saved in its widest mode with a simple SET insn as long as the memory
+ address is valid. We record the INSN_CODE is those insns here since
+ when we emit them, the addresses might not be valid, so they might not
+ be recognized. */
+ int x_cached_reg_save_code[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
+ int x_cached_reg_restore_code[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
+};
-/* Element N is the list of insns that initialized reg N from its equivalent
- constant or memory slot. */
-extern GTY((length("reg_equiv_init_size"))) rtx *reg_equiv_init;
+extern struct target_reload default_target_reload;
+#if SWITCHABLE_TARGET
+extern struct target_reload *this_target_reload;
+#else
+#define this_target_reload (&default_target_reload)
+#endif
-/* The size of the previous array, for GC purposes. */
-extern GTY(()) int reg_equiv_init_size;
+#define indirect_symref_ok \
+ (this_target_reload->x_indirect_symref_ok)
+#define double_reg_address_ok \
+ (this_target_reload->x_double_reg_address_ok)
+#define caller_save_initialized_p \
+ (this_target_reload->x_caller_save_initialized_p)
+
+/* Register equivalences. Indexed by register number. */
+typedef struct reg_equivs
+{
+ /* The constant value to which pseudo reg N is equivalent,
+ or zero if pseudo reg N is not equivalent to a constant.
+ find_reloads looks at this in order to replace pseudo reg N
+ with the constant it stands for. */
+ rtx constant;
+
+ /* An invariant value to which pseudo reg N is equivalent.
+ eliminate_regs_in_insn uses this to replace pseudos in particular
+ contexts. */
+ rtx invariant;
+
+ /* A memory location to which pseudo reg N is equivalent,
+ prior to any register elimination (such as frame pointer to stack
+ pointer). Depending on whether or not it is a valid address, this value
+ is transferred to either equiv_address or equiv_mem. */
+ rtx memory_loc;
+
+ /* The address of stack slot to which pseudo reg N is equivalent.
+ This is used when the address is not valid as a memory address
+ (because its displacement is too big for the machine.) */
+ rtx address;
+
+ /* The memory slot to which pseudo reg N is equivalent,
+ or zero if pseudo reg N is not equivalent to a memory slot. */
+ rtx mem;
+
+ /* An EXPR_LIST of REG_EQUIVs containing MEMs with
+ alternate representations of the location of pseudo reg N. */
+ rtx alt_mem_list;
+
+ /* The list of insns that initialized reg N from its equivalent
+ constant or memory slot. */
+ rtx init;
+} reg_equivs_t;
+
+#define reg_equiv_constant(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->constant
+#define reg_equiv_invariant(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->invariant
+#define reg_equiv_memory_loc(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->memory_loc
+#define reg_equiv_address(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->address
+#define reg_equiv_mem(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->mem
+#define reg_equiv_alt_mem_list(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->alt_mem_list
+#define reg_equiv_init(ELT) \
+ VEC_index (reg_equivs_t, reg_equivs, (ELT))->init
+
+DEF_VEC_O(reg_equivs_t);
+DEF_VEC_ALLOC_O(reg_equivs_t, gc);
+extern VEC(reg_equivs_t,gc) *reg_equivs;
/* All the "earlyclobber" operands of the current insn
are recorded here. */
Used in find_equiv_reg. */
extern int reload_first_uid;
-/* Nonzero if indirect addressing is supported when the innermost MEM is
- of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
- which these are valid is the same as spill_indirect_levels, above. */
-
-extern char indirect_symref_ok;
-
-/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
-extern char double_reg_address_ok;
-
extern int num_not_at_initial_offset;
#if defined SET_HARD_REG_BIT && defined CLEAR_REG_SET
/* Functions from reload.c: */
-extern enum reg_class secondary_reload_class (bool, enum reg_class,
- enum machine_mode, rtx);
+extern reg_class_t secondary_reload_class (bool, reg_class_t,
+ enum machine_mode, rtx);
#ifdef GCC_INSN_CODES_H
extern enum reg_class scratch_reload_class (enum insn_code);
extern void init_reload (void);
/* The reload pass itself. */
-extern int reload (rtx, int);
+extern bool reload (rtx, int);
/* Mark the slots in regs_ever_live for the hard regs
used by pseudo-reg number REGNO. */
/* Deallocate the reload register used by reload number R. */
extern void deallocate_reload_reg (int r);
-/* True if caller-save has been reinitialized. */
-extern bool caller_save_initialized_p;
-
/* Functions in caller-save.c: */
/* Initialize for caller-save. */
/* Compute the actual register we should reload to, in case we're
reloading to/from a register that is wider than a word. */
extern rtx reload_adjust_reg_for_mode (rtx, enum machine_mode);
+
+/* Ideally this function would be in ira.c or reload, but due to dependencies
+ on integrate.h, it's part of integrate.c. */
+extern void allocate_initial_values (VEC (reg_equivs_t, gc) *);
+
+/* Allocate or grow the reg_equiv tables, initializing new entries to 0. */
+extern void grow_reg_equivs (void);
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