#include "function.h"
#include "toplev.h"
-#ifndef REGISTER_MOVE_COST
-#define REGISTER_MOVE_COST(m, x, y) 2
-#endif
-
#ifndef REGNO_MODE_OK_FOR_BASE_P
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO)
#endif
!= (int) HARD_REGNO_NREGS (REGNO (inner), GET_MODE (inner))));
}
+/* Return nonzero if IN can be reloaded into REGNO with mode MODE without
+ requiring an extra reload register. The caller has already found that
+ IN contains some reference to REGNO, so check that we can produce the
+ new value in a single step. E.g. if we have
+ (set (reg r13) (plus (reg r13) (const int 1))), and there is an
+ instruction that adds one to a register, this should succeed.
+ However, if we have something like
+ (set (reg r13) (plus (reg r13) (const int 999))), and the constant 999
+ needs to be loaded into a register first, we need a separate reload
+ register.
+ Such PLUS reloads are generated by find_reload_address_part.
+ The out-of-range PLUS expressions are usually introduced in the instruction
+ patterns by register elimination and substituting pseudos without a home
+ by their function-invariant equivalences. */
+static int
+can_reload_into (rtx in, int regno, enum machine_mode mode)
+{
+ rtx dst, test_insn;
+ int r = 0;
+ struct recog_data save_recog_data;
+
+ /* For matching constraints, we often get notional input reloads where
+ we want to use the original register as the reload register. I.e.
+ technically this is a non-optional input-output reload, but IN is
+ already a valid register, and has been chosen as the reload register.
+ Speed this up, since it trivially works. */
+ if (GET_CODE (in) == REG)
+ return 1;
+
+ /* To test MEMs properly, we'd have to take into account all the reloads
+ that are already scheduled, which can become quite complicated.
+ And since we've already handled address reloads for this MEM, it
+ should always succeed anyway. */
+ if (GET_CODE (in) == MEM)
+ return 1;
+
+ /* If we can make a simple SET insn that does the job, everything should
+ be fine. */
+ dst = gen_rtx_REG (mode, regno);
+ test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in));
+ save_recog_data = recog_data;
+ if (recog_memoized (test_insn) >= 0)
+ {
+ extract_insn (test_insn);
+ r = constrain_operands (1);
+ }
+ recog_data = save_recog_data;
+ return r;
+}
+
/* Record one reload that needs to be performed.
IN is an rtx saying where the data are to be found before this instruction.
OUT says where they must be stored after the instruction.
regno + offs))
break;
- if (offs == nregs)
+ if (offs == nregs
+ && (! (refers_to_regno_for_reload_p
+ (regno, (regno + HARD_REGNO_NREGS (regno, inmode)),
+ in, (rtx *)0))
+ || can_reload_into (in, regno, inmode)))
{
rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno);
break;
if (GET_CODE (SUBREG_REG (operand)) == REG
&& REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER)
{
+ if (!subreg_offset_representable_p
+ (REGNO (SUBREG_REG (operand)),
+ GET_MODE (SUBREG_REG (operand)),
+ SUBREG_BYTE (operand),
+ GET_MODE (operand)))
+ force_reload = 1;
offset += subreg_regno_offset (REGNO (SUBREG_REG (operand)),
GET_MODE (SUBREG_REG (operand)),
SUBREG_BYTE (operand),
)
#endif
)
- /* This following hunk of code should no longer be
- needed at all with SUBREG_BYTE. If you need this
- code back, please explain to me why so I can
- fix the real problem. -DaveM */
-#if 0
- /* Subreg of a hard reg which can't handle the subreg's mode
- or which would handle that mode in the wrong number of
- registers for subregging to work. */
- || (GET_CODE (operand) == REG
- && REGNO (operand) < FIRST_PSEUDO_REGISTER
- && ((GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
- && (GET_MODE_SIZE (GET_MODE (operand))
- > UNITS_PER_WORD)
- && ((GET_MODE_SIZE (GET_MODE (operand))
- / UNITS_PER_WORD)
- != HARD_REGNO_NREGS (REGNO (operand),
- GET_MODE (operand))))
- || ! HARD_REGNO_MODE_OK (REGNO (operand) + offset,
- operand_mode[i])))
-#endif
)
force_reload = 1;
}
if (regno < FIRST_PSEUDO_REGISTER
&& TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno)
&& HARD_REGNO_MODE_OK (regno, rld[i].mode))
- rld[i].reg_rtx = dest;
+ {
+ int nr = HARD_REGNO_NREGS (regno, rld[i].mode);
+ int ok = 1, nri;
+
+ for (nri = 1; nri < nr; nri ++)
+ if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno + nri))
+ ok = 0;
+
+ if (ok)
+ rld[i].reg_rtx = dest;
+ }
}
return retval;
of it.
Handle all base registers here, not just fp/ap/sp, because on some
- targets (namely Sparc) we can also get invalid addresses from preventive
+ targets (namely SPARC) we can also get invalid addresses from preventive
subreg big-endian corrections made by find_reloads_toplev.
If we decide to do something, it must be that `double_reg_address_ok'
SUBREG_BYTE (orig_op1),
GET_MODE (orig_op1))));
}
+ /* Plus in the index register may be created only as a result of
+ register remateralization for expresion like &localvar*4. Reload it.
+ It may be possible to combine the displacement on the outer level,
+ but it is probably not worthwhile to do so. */
+ if (context)
+ {
+ find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
+ opnum, ADDR_TYPE (type), ind_levels, insn);
+ push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
+ (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
+ GET_MODE (x), VOIDmode, 0, 0, opnum, type);
+ return 1;
+ }
if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
|| code0 == ZERO_EXTEND || code1 == MEM)
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