/* Subroutines used by or related to instruction recognition.
- Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc.
+ Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
+ 1999, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
#include "config.h"
+#include "system.h"
#include "rtl.h"
-#include <stdio.h>
+#include "tm_p.h"
#include "insn-config.h"
#include "insn-attr.h"
#include "insn-flags.h"
#include "insn-codes.h"
+#include "hard-reg-set.h"
#include "recog.h"
#include "regs.h"
-#include "hard-reg-set.h"
+#include "function.h"
#include "flags.h"
#include "real.h"
+#include "toplev.h"
+#include "basic-block.h"
+#include "output.h"
+#include "reload.h"
#ifndef STACK_PUSH_CODE
#ifdef STACK_GROWS_DOWNWARD
#endif
#endif
-/* Import from final.c: */
-extern rtx alter_subreg ();
+#ifndef STACK_POP_CODE
+#ifdef STACK_GROWS_DOWNWARD
+#define STACK_POP_CODE POST_INC
+#else
+#define STACK_POP_CODE POST_DEC
+#endif
+#endif
-int strict_memory_address_p ();
-int memory_address_p ();
+static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
+static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
+static rtx *find_constant_term_loc PARAMS ((rtx *));
+static int insn_invalid_p PARAMS ((rtx));
/* Nonzero means allow operands to be volatile.
This should be 0 if you are generating rtl, such as if you are calling
int volatile_ok;
+struct recog_data recog_data;
+
+/* Contains a vector of operand_alternative structures for every operand.
+ Set up by preprocess_constraints. */
+struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
+
/* On return from `constrain_operands', indicate which alternative
was satisfied. */
/* Try recognizing the instruction INSN,
and return the code number that results.
- Remeber the code so that repeated calls do not
+ Remember the code so that repeated calls do not
need to spend the time for actual rerecognition.
This function is the normal interface to instruction recognition.
through this one. (The only exception is in combine.c.) */
int
-recog_memoized (insn)
+recog_memoized_1 (insn)
rtx insn;
{
if (INSN_CODE (insn) < 0)
check_asm_operands (x)
rtx x;
{
- int noperands = asm_noperands (x);
+ int noperands;
rtx *operands;
+ const char **constraints;
int i;
+ /* Post-reload, be more strict with things. */
+ if (reload_completed)
+ {
+ /* ??? Doh! We've not got the wrapping insn. Cook one up. */
+ extract_insn (make_insn_raw (x));
+ constrain_operands (1);
+ return which_alternative >= 0;
+ }
+
+ noperands = asm_noperands (x);
if (noperands < 0)
return 0;
if (noperands == 0)
return 1;
operands = (rtx *) alloca (noperands * sizeof (rtx));
- decode_asm_operands (x, operands, NULL_PTR, NULL_PTR, NULL_PTR);
+ constraints = (const char **) alloca (noperands * sizeof (char *));
+
+ decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR);
for (i = 0; i < noperands; i++)
- if (!general_operand (operands[i], VOIDmode))
- return 0;
+ {
+ const char *c = constraints[i];
+ if (c[0] == '%')
+ c++;
+ if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0')
+ c = constraints[c[0] - '0'];
+
+ if (! asm_operand_ok (operands[i], c))
+ return 0;
+ }
return 1;
}
\f
-/* Static data for the next two routines.
+/* Static data for the next two routines. */
- The maximum number of changes supported is defined as the maximum
- number of operands times 5. This allows for repeated substitutions
- inside complex indexed address, or, alternatively, changes in up
- to 5 insns. */
-
-#define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5)
+typedef struct change_t
+{
+ rtx object;
+ int old_code;
+ rtx *loc;
+ rtx old;
+} change_t;
-static rtx change_objects[MAX_CHANGE_LOCS];
-static int change_old_codes[MAX_CHANGE_LOCS];
-static rtx *change_locs[MAX_CHANGE_LOCS];
-static rtx change_olds[MAX_CHANGE_LOCS];
+static change_t *changes;
+static int changes_allocated;
static int num_changes = 0;
if (old == new || rtx_equal_p (old, new))
return 1;
- if (num_changes >= MAX_CHANGE_LOCS
- || (in_group == 0 && num_changes != 0))
+ if (in_group == 0 && num_changes != 0)
abort ();
*loc = new;
/* Save the information describing this change. */
- change_objects[num_changes] = object;
- change_locs[num_changes] = loc;
- change_olds[num_changes] = old;
+ if (num_changes >= changes_allocated)
+ {
+ if (changes_allocated == 0)
+ /* This value allows for repeated substitutions inside complex
+ indexed addresses, or changes in up to 5 insns. */
+ changes_allocated = MAX_RECOG_OPERANDS * 5;
+ else
+ changes_allocated *= 2;
+
+ changes =
+ (change_t*) xrealloc (changes,
+ sizeof (change_t) * changes_allocated);
+ }
+
+ changes[num_changes].object = object;
+ changes[num_changes].loc = loc;
+ changes[num_changes].old = old;
if (object && GET_CODE (object) != MEM)
{
/* Set INSN_CODE to force rerecognition of insn. Save old code in
case invalid. */
- change_old_codes[num_changes] = INSN_CODE (object);
+ changes[num_changes].old_code = INSN_CODE (object);
INSN_CODE (object) = -1;
}
return apply_change_group ();
}
+/* This subroutine of apply_change_group verifies whether the changes to INSN
+ were valid; i.e. whether INSN can still be recognized. */
+
+static int
+insn_invalid_p (insn)
+ rtx insn;
+{
+ int icode = recog_memoized (insn);
+ int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
+
+ if (is_asm && ! check_asm_operands (PATTERN (insn)))
+ return 1;
+ if (! is_asm && icode < 0)
+ return 1;
+
+ /* After reload, verify that all constraints are satisfied. */
+ if (reload_completed)
+ {
+ extract_insn (insn);
+
+ if (! constrain_operands (1))
+ return 1;
+ }
+
+ return 0;
+}
+
/* Apply a group of changes previously issued with `validate_change'.
Return 1 if all changes are valid, zero otherwise. */
given a MEM and it still is a valid address, or if this is in insn
and it is recognized. In the latter case, if reload has completed,
we also require that the operands meet the constraints for
- the insn. We do not allow modifying an ASM_OPERANDS after reload
- has completed because verifying the constraints is too difficult. */
+ the insn. */
for (i = 0; i < num_changes; i++)
{
- rtx object = change_objects[i];
+ rtx object = changes[i].object;
if (object == 0)
continue;
if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
break;
}
- else if ((recog_memoized (object) < 0
- && (asm_noperands (PATTERN (object)) < 0
- || ! check_asm_operands (PATTERN (object))
- || reload_completed))
- || (reload_completed
- && (insn_extract (object),
- ! constrain_operands (INSN_CODE (object), 1))))
+ else if (insn_invalid_p (object))
{
rtx pat = PATTERN (object);
{
int j;
- newpat = gen_rtx (PARALLEL, VOIDmode,
- gen_rtvec (XVECLEN (pat, 0) - 1));
+ newpat
+ = gen_rtx_PARALLEL (VOIDmode,
+ rtvec_alloc (XVECLEN (pat, 0) - 1));
for (j = 0; j < XVECLEN (newpat, 0); j++)
XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
}
they were made. */
for (i = num_changes - 1; i >= num; i--)
{
- *change_locs[i] = change_olds[i];
- if (change_objects[i] && GET_CODE (change_objects[i]) != MEM)
- INSN_CODE (change_objects[i]) = change_old_codes[i];
+ *changes[i].loc = changes[i].old;
+ if (changes[i].object && GET_CODE (changes[i].object) != MEM)
+ INSN_CODE (changes[i].object) = changes[i].old_code;
}
num_changes = num;
}
rtx from, to, object;
{
register int i, j;
- register char *fmt;
+ register const char *fmt;
register rtx x = *loc;
- enum rtx_code code = GET_CODE (x);
+ enum rtx_code code;
+ if (!x)
+ return;
+ code = GET_CODE (x);
/* X matches FROM if it is the same rtx or they are both referring to the
same register in the same mode. Avoid calling rtx_equal_p unless the
operands look similar. */
if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
{
validate_change (object, loc,
- gen_rtx (GET_RTX_CLASS (code) == 'c' ? code
- : swap_condition (code),
- GET_MODE (x), XEXP (x, 1), XEXP (x, 0)),
+ gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
+ : swap_condition (code),
+ GET_MODE (x), XEXP (x, 1),
+ XEXP (x, 0)),
1);
x = *loc;
code = GET_CODE (x);
}
}
+ /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
+ done the substitution, otherwise we won't. */
+
switch (code)
{
case PLUS:
- /* If we have have a PLUS whose second operand is now a CONST_INT, use
+ /* If we have a PLUS whose second operand is now a CONST_INT, use
plus_constant to try to simplify it. */
if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
- validate_change (object, loc,
- plus_constant (XEXP (x, 0), INTVAL (XEXP (x, 1))), 1);
+ validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
+ 1);
return;
+
+ case MINUS:
+ if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
+ {
+ validate_change (object, loc,
+ plus_constant (XEXP (x, 0), - INTVAL (to)),
+ 1);
+ return;
+ }
+ break;
case ZERO_EXTEND:
case SIGN_EXTEND:
/* In these cases, the operation to be performed depends on the mode
of the operand. If we are replacing the operand with a VOIDmode
constant, we lose the information. So try to simplify the operation
- in that case. If it fails, substitute in something that we know
- won't be recognized. */
+ in that case. */
if (GET_MODE (to) == VOIDmode
- && (XEXP (x, 0) == from
- || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG
- && GET_MODE (XEXP (x, 0)) == GET_MODE (from)
- && REGNO (XEXP (x, 0)) == REGNO (from))))
+ && (rtx_equal_p (XEXP (x, 0), from)
+ || (GET_CODE (XEXP (x, 0)) == SUBREG
+ && rtx_equal_p (SUBREG_REG (XEXP (x, 0)), from))))
{
- rtx new = simplify_unary_operation (code, GET_MODE (x), to,
- GET_MODE (from));
- if (new == 0)
- new = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
+ rtx new = NULL_RTX;
+
+ /* If there is a subreg involved, crop to the portion of the
+ constant that we are interested in. */
+ if (GET_CODE (XEXP (x, 0)) == SUBREG)
+ to = operand_subword (to, SUBREG_WORD (XEXP (x, 0)),
+ 0, GET_MODE (from));
+
+ /* If the above didn't fail, perform the extension from the
+ mode of the operand (and not the mode of FROM). */
+ if (to)
+ new = simplify_unary_operation (code, GET_MODE (x), to,
+ GET_MODE (XEXP (x, 0)));
+
+ /* If any of the above failed, substitute in something that
+ we know won't be recognized. */
+ if (!new)
+ new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
validate_change (object, loc, new, 1);
return;
break;
case SUBREG:
+ /* In case we are replacing by constant, attempt to simplify it to non-SUBREG
+ expression. We can't do this later, since the information about inner mode
+ may be lost. */
+ if (CONSTANT_P (to) && rtx_equal_p (SUBREG_REG (x), from))
+ {
+ if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD
+ && GET_MODE_SIZE (GET_MODE (from)) > UNITS_PER_WORD
+ && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
+ {
+ rtx temp = operand_subword (to, SUBREG_WORD (x),
+ 0, GET_MODE (from));
+ if (temp)
+ {
+ validate_change (object, loc, temp, 1);
+ return;
+ }
+ }
+ if (subreg_lowpart_p (x))
+ {
+ rtx new = gen_lowpart_if_possible (GET_MODE (x), to);
+ if (new)
+ {
+ validate_change (object, loc, new, 1);
+ return;
+ }
+ }
+
+ /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
+ since we are saying that the high bits don't matter. */
+ if (GET_MODE (to) == VOIDmode
+ && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (from)))
+ {
+ validate_change (object, loc, to, 1);
+ return;
+ }
+ }
+
+ /* Changing mode twice with SUBREG => just change it once,
+ or not at all if changing back to starting mode. */
+ if (GET_CODE (to) == SUBREG
+ && rtx_equal_p (SUBREG_REG (x), from))
+ {
+ if (GET_MODE (x) == GET_MODE (SUBREG_REG (to))
+ && SUBREG_WORD (x) == 0 && SUBREG_WORD (to) == 0)
+ {
+ validate_change (object, loc, SUBREG_REG (to), 1);
+ return;
+ }
+
+ validate_change (object, loc,
+ gen_rtx_SUBREG (GET_MODE (x), SUBREG_REG (to),
+ SUBREG_WORD (x) + SUBREG_WORD (to)), 1);
+ return;
+ }
+
/* If we have a SUBREG of a register that we are replacing and we are
replacing it with a MEM, make a new MEM and try replacing the
SUBREG with it. Don't do this if the MEM has a mode-dependent address
or if we would be widening it. */
- if (SUBREG_REG (x) == from
- && GET_CODE (from) == REG
+ if (GET_CODE (from) == REG
&& GET_CODE (to) == MEM
+ && rtx_equal_p (SUBREG_REG (x), from)
&& ! mode_dependent_address_p (XEXP (to, 0))
&& ! MEM_VOLATILE_P (to)
&& GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
enum machine_mode mode = GET_MODE (x);
rtx new;
-#if BYTES_BIG_ENDIAN
- offset += (MIN (UNITS_PER_WORD,
- GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
- - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
-#endif
+ if (BYTES_BIG_ENDIAN)
+ offset += (MIN (UNITS_PER_WORD,
+ GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
+ - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
- new = gen_rtx (MEM, mode, plus_constant (XEXP (to, 0), offset));
- MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to);
- RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to);
- MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to);
+ new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
+ MEM_COPY_ATTRIBUTES (new, to);
validate_change (object, loc, new, 1);
return;
}
likely to be an insertion operation; if it was, nothing bad will
happen, we might just fail in some cases). */
- if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM
+ if (GET_CODE (from) == REG && GET_CODE (to) == MEM
+ && rtx_equal_p (XEXP (x, 0), from)
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& GET_CODE (XEXP (x, 2)) == CONST_INT
&& ! mode_dependent_address_p (XEXP (to, 0))
{
enum machine_mode wanted_mode = VOIDmode;
enum machine_mode is_mode = GET_MODE (to);
- int width = INTVAL (XEXP (x, 1));
int pos = INTVAL (XEXP (x, 2));
#ifdef HAVE_extzv
if (code == ZERO_EXTRACT)
- wanted_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
+ {
+ wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
+ if (wanted_mode == VOIDmode)
+ wanted_mode = word_mode;
+ }
#endif
#ifdef HAVE_extv
if (code == SIGN_EXTRACT)
- wanted_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
+ {
+ wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode;
+ if (wanted_mode == VOIDmode)
+ wanted_mode = word_mode;
+ }
#endif
/* If we have a narrower mode, we can do something. */
/* If the bytes and bits are counted differently, we
must adjust the offset. */
-#if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
- offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
- - offset);
-#endif
+ if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
+ offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
+ - offset);
pos %= GET_MODE_BITSIZE (wanted_mode);
- newmem = gen_rtx (MEM, wanted_mode,
- plus_constant (XEXP (to, 0), offset));
- RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to);
- MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (to);
- MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (to);
+ newmem = gen_rtx_MEM (wanted_mode,
+ plus_constant (XEXP (to, 0), offset));
+ MEM_COPY_ATTRIBUTES (newmem, to);
validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
validate_change (object, &XEXP (x, 0), newmem, 1);
}
break;
+
+ default:
+ break;
}
- fmt = GET_RTX_FORMAT (code);
- for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ /* For commutative or comparison operations we've already performed
+ replacements. Don't try to perform them again. */
+ if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
{
- if (fmt[i] == 'e')
- validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
- else if (fmt[i] == 'E')
- for (j = XVECLEN (x, i) - 1; j >= 0; j--)
- validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
+ fmt = GET_RTX_FORMAT (code);
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ {
+ if (fmt[i] == 'e')
+ validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
+ else if (fmt[i] == 'E')
+ for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+ validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
+ }
}
}
+/* Try replacing every occurrence of FROM in subexpression LOC of INSN
+ with TO. After all changes have been made, validate by seeing
+ if INSN is still valid. */
+
+int
+validate_replace_rtx_subexp (from, to, insn, loc)
+ rtx from, to, insn, *loc;
+{
+ validate_replace_rtx_1 (loc, from, to, insn);
+ return apply_change_group ();
+}
+
/* Try replacing every occurrence of FROM in INSN with TO. After all
changes have been made, validate by seeing if INSN is still valid. */
validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
return apply_change_group ();
}
+
+/* Try replacing every occurrence of FROM in INSN with TO. After all
+ changes have been made, validate by seeing if INSN is still valid. */
+
+void
+validate_replace_rtx_group (from, to, insn)
+ rtx from, to, insn;
+{
+ validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
+}
+
+/* Try replacing every occurrence of FROM in INSN with TO, avoiding
+ SET_DESTs. After all changes have been made, validate by seeing if
+ INSN is still valid. */
+
+int
+validate_replace_src (from, to, insn)
+ rtx from, to, insn;
+{
+ if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
+ || GET_CODE (PATTERN (insn)) != SET)
+ abort ();
+
+ validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn);
+ if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
+ validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0),
+ from, to, insn);
+ return apply_change_group ();
+}
\f
#ifdef HAVE_cc0
/* Return 1 if the insn using CC0 set by INSN does not contain
rtx *result = 0;
rtx *this_result;
int i;
- char *fmt;
+ const char *fmt;
switch (code)
{
case MEM:
case SUBREG:
return find_single_use_1 (dest, &XEXP (x, 0));
+
+ default:
+ break;
}
/* If it wasn't one of the common cases above, check each expression and
for (next = next_nonnote_insn (insn);
next != 0 && GET_CODE (next) != CODE_LABEL;
next = next_nonnote_insn (next))
- if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest))
+ if (INSN_P (next) && dead_or_set_p (next, dest))
{
for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
if (XEXP (link, 0) == insn)
return 0;
if (CONSTANT_P (op))
- return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
+ return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
+ || mode == VOIDmode)
#ifdef LEGITIMATE_PIC_OPERAND_P
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
#endif
if (code == MEM)
{
register rtx y = XEXP (op, 0);
+
if (! volatile_ok && MEM_VOLATILE_P (op))
return 0;
+
+ if (GET_CODE (y) == ADDRESSOF)
+ return 1;
+
/* Use the mem's mode, since it will be reloaded thus. */
mode = GET_MODE (op);
GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
}
+
+ /* Pretend this is an operand for now; we'll run force_operand
+ on its replacement in fixup_var_refs_1. */
+ if (code == ADDRESSOF)
+ return 1;
+
return 0;
win:
reg went on the stack.) */
if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
return general_operand (op, mode);
+
+#ifdef CLASS_CANNOT_CHANGE_MODE
+ if (GET_CODE (SUBREG_REG (op)) == REG
+ && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
+ && (TEST_HARD_REG_BIT
+ (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
+ REGNO (SUBREG_REG (op))))
+ && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
+ && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
+ && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
+ return 0;
+#endif
+
op = SUBREG_REG (op);
}
+ /* If we have an ADDRESSOF, consider it valid since it will be
+ converted into something that will not be a MEM. */
+ if (GET_CODE (op) == ADDRESSOF)
+ return 1;
+
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
return (GET_CODE (op) == REG
|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
}
+/* Return 1 for a register in Pmode; ignore the tested mode. */
+
+int
+pmode_register_operand (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ return register_operand (op, Pmode);
+}
+
/* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
or a hard register. */
register rtx op;
enum machine_mode mode;
{
- return (GET_MODE (op) == mode
- && (GET_CODE (op) == SCRATCH
- || (GET_CODE (op) == REG
- && REGNO (op) < FIRST_PSEUDO_REGISTER)));
+ if (GET_MODE (op) != mode && mode != VOIDmode)
+ return 0;
+
+ return (GET_CODE (op) == SCRATCH
+ || (GET_CODE (op) == REG
+ && REGNO (op) < FIRST_PSEUDO_REGISTER));
}
/* Return 1 if OP is a valid immediate operand for mode MODE.
&& GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
return 0;
+ /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
+ result in 0/1. It seems a safe assumption that this is
+ in range for everyone. */
+ if (GET_CODE (op) == CONSTANT_P_RTX)
+ return 1;
+
return (CONSTANT_P (op)
&& (GET_MODE (op) == mode || mode == VOIDmode
|| GET_MODE (op) == VOIDmode)
int
const_int_operand (op, mode)
register rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return GET_CODE (op) == CONST_INT;
}
&& GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
return 0;
- return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
+ return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
+ || mode == VOIDmode)
#ifdef LEGITIMATE_PIC_OPERAND_P
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
#endif
if (GET_CODE (op) != MEM)
return 0;
- if (GET_MODE (op) != mode)
+ if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
op = XEXP (op, 0);
return XEXP (op, 0) == stack_pointer_rtx;
}
+/* Return 1 if OP is a valid operand that stands for popping a
+ value of mode MODE off the stack.
+
+ The main use of this function is as a predicate in match_operand
+ expressions in the machine description. */
+
+int
+pop_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+{
+ if (GET_CODE (op) != MEM)
+ return 0;
+
+ if (mode != VOIDmode && GET_MODE (op) != mode)
+ return 0;
+
+ op = XEXP (op, 0);
+
+ if (GET_CODE (op) != STACK_POP_CODE)
+ return 0;
+
+ return XEXP (op, 0) == stack_pointer_rtx;
+}
+
/* Return 1 if ADDR is a valid memory address for mode MODE. */
int
memory_address_p (mode, addr)
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
register rtx addr;
{
+ if (GET_CODE (addr) == ADDRESSOF)
+ return 1;
+
GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
return 0;
register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
rtx inner = SUBREG_REG (op);
-#if BYTES_BIG_ENDIAN
- offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
- - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
-#endif
+ if (BYTES_BIG_ENDIAN)
+ offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
+ - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
asm_noperands (body)
rtx body;
{
- if (GET_CODE (body) == ASM_OPERANDS)
- /* No output operands: return number of input operands. */
- return ASM_OPERANDS_INPUT_LENGTH (body);
- if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
- /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
- return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
- else if (GET_CODE (body) == PARALLEL
- && GET_CODE (XVECEXP (body, 0, 0)) == SET
- && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
+ switch (GET_CODE (body))
{
- /* Multiple output operands, or 1 output plus some clobbers:
- body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
- int i;
- int n_sets;
-
- /* Count backwards through CLOBBERs to determine number of SETs. */
- for (i = XVECLEN (body, 0); i > 0; i--)
+ case ASM_OPERANDS:
+ /* No output operands: return number of input operands. */
+ return ASM_OPERANDS_INPUT_LENGTH (body);
+ case SET:
+ if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
+ /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
+ return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
+ else
+ return -1;
+ case PARALLEL:
+ if (GET_CODE (XVECEXP (body, 0, 0)) == SET
+ && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
{
- if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
- break;
- if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
- return -1;
- }
+ /* Multiple output operands, or 1 output plus some clobbers:
+ body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
+ int i;
+ int n_sets;
+
+ /* Count backwards through CLOBBERs to determine number of SETs. */
+ for (i = XVECLEN (body, 0); i > 0; i--)
+ {
+ if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
+ break;
+ if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
+ return -1;
+ }
- /* N_SETS is now number of output operands. */
- n_sets = i;
+ /* N_SETS is now number of output operands. */
+ n_sets = i;
- /* Verify that all the SETs we have
- came from a single original asm_operands insn
- (so that invalid combinations are blocked). */
- for (i = 0; i < n_sets; i++)
- {
- rtx elt = XVECEXP (body, 0, i);
- if (GET_CODE (elt) != SET)
- return -1;
- if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
- return -1;
- /* If these ASM_OPERANDS rtx's came from different original insns
- then they aren't allowed together. */
- if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
- != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
- return -1;
+ /* Verify that all the SETs we have
+ came from a single original asm_operands insn
+ (so that invalid combinations are blocked). */
+ for (i = 0; i < n_sets; i++)
+ {
+ rtx elt = XVECEXP (body, 0, i);
+ if (GET_CODE (elt) != SET)
+ return -1;
+ if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
+ return -1;
+ /* If these ASM_OPERANDS rtx's came from different original insns
+ then they aren't allowed together. */
+ if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
+ != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
+ return -1;
+ }
+ return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
+ + n_sets);
}
- return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
- + n_sets);
- }
- else if (GET_CODE (body) == PARALLEL
- && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
- {
- /* 0 outputs, but some clobbers:
- body is [(asm_operands ...) (clobber (reg ...))...]. */
- int i;
+ else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
+ {
+ /* 0 outputs, but some clobbers:
+ body is [(asm_operands ...) (clobber (reg ...))...]. */
+ int i;
- /* Make sure all the other parallel things really are clobbers. */
- for (i = XVECLEN (body, 0) - 1; i > 0; i--)
- if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
- return -1;
+ /* Make sure all the other parallel things really are clobbers. */
+ for (i = XVECLEN (body, 0) - 1; i > 0; i--)
+ if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
+ return -1;
- return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
+ return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
+ }
+ else
+ return -1;
+ default:
+ return -1;
}
- else
- return -1;
}
/* Assuming BODY is an insn body that uses ASM_OPERANDS,
If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
we don't store that info. */
-char *
+const char *
decode_asm_operands (body, operands, operand_locs, constraints, modes)
rtx body;
rtx *operands;
rtx **operand_locs;
- char **constraints;
+ const char **constraints;
enum machine_mode *modes;
{
register int i;
int noperands;
- char *template = 0;
+ const char *template = 0;
if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
{
return template;
}
+
+/* Check if an asm_operand matches it's constraints.
+ Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
+
+int
+asm_operand_ok (op, constraint)
+ rtx op;
+ const char *constraint;
+{
+ int result = 0;
+
+ /* Use constrain_operands after reload. */
+ if (reload_completed)
+ abort ();
+
+ while (*constraint)
+ {
+ char c = *constraint++;
+ switch (c)
+ {
+ case '=':
+ case '+':
+ case '*':
+ case '%':
+ case '?':
+ case '!':
+ case '#':
+ case '&':
+ case ',':
+ break;
+
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ /* For best results, our caller should have given us the
+ proper matching constraint, but we can't actually fail
+ the check if they didn't. Indicate that results are
+ inconclusive. */
+ result = -1;
+ break;
+
+ case 'p':
+ if (address_operand (op, VOIDmode))
+ return 1;
+ break;
+
+ case 'm':
+ case 'V': /* non-offsettable */
+ if (memory_operand (op, VOIDmode))
+ return 1;
+ break;
+
+ case 'o': /* offsettable */
+ if (offsettable_nonstrict_memref_p (op))
+ return 1;
+ break;
+
+ case '<':
+ /* ??? Before flow, auto inc/dec insns are not supposed to exist,
+ excepting those that expand_call created. Further, on some
+ machines which do not have generalized auto inc/dec, an inc/dec
+ is not a memory_operand.
+
+ Match any memory and hope things are resolved after reload. */
+
+ if (GET_CODE (op) == MEM
+ && (1
+ || GET_CODE (XEXP (op, 0)) == PRE_DEC
+ || GET_CODE (XEXP (op, 0)) == POST_DEC))
+ return 1;
+ break;
+
+ case '>':
+ if (GET_CODE (op) == MEM
+ && (1
+ || GET_CODE (XEXP (op, 0)) == PRE_INC
+ || GET_CODE (XEXP (op, 0)) == POST_INC))
+ return 1;
+ break;
+
+ case 'E':
+#ifndef REAL_ARITHMETIC
+ /* Match any floating double constant, but only if
+ we can examine the bits of it reliably. */
+ if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
+ || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
+ && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
+ break;
+#endif
+ /* FALLTHRU */
+
+ case 'F':
+ if (GET_CODE (op) == CONST_DOUBLE)
+ return 1;
+ break;
+
+ case 'G':
+ if (GET_CODE (op) == CONST_DOUBLE
+ && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
+ return 1;
+ break;
+ case 'H':
+ if (GET_CODE (op) == CONST_DOUBLE
+ && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
+ return 1;
+ break;
+
+ case 's':
+ if (GET_CODE (op) == CONST_INT
+ || (GET_CODE (op) == CONST_DOUBLE
+ && GET_MODE (op) == VOIDmode))
+ break;
+ /* FALLTHRU */
+
+ case 'i':
+ if (CONSTANT_P (op)
+#ifdef LEGITIMATE_PIC_OPERAND_P
+ && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+#endif
+ )
+ return 1;
+ break;
+
+ case 'n':
+ if (GET_CODE (op) == CONST_INT
+ || (GET_CODE (op) == CONST_DOUBLE
+ && GET_MODE (op) == VOIDmode))
+ return 1;
+ break;
+
+ case 'I':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
+ return 1;
+ break;
+ case 'J':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
+ return 1;
+ break;
+ case 'K':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
+ return 1;
+ break;
+ case 'L':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
+ return 1;
+ break;
+ case 'M':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
+ return 1;
+ break;
+ case 'N':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
+ return 1;
+ break;
+ case 'O':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
+ return 1;
+ break;
+ case 'P':
+ if (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
+ return 1;
+ break;
+
+ case 'X':
+ return 1;
+
+ case 'g':
+ if (general_operand (op, VOIDmode))
+ return 1;
+ break;
+
+ default:
+ /* For all other letters, we first check for a register class,
+ otherwise it is an EXTRA_CONSTRAINT. */
+ if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
+ {
+ case 'r':
+ if (GET_MODE (op) == BLKmode)
+ break;
+ if (register_operand (op, VOIDmode))
+ return 1;
+ }
+#ifdef EXTRA_CONSTRAINT
+ if (EXTRA_CONSTRAINT (op, c))
+ return 1;
+#endif
+ break;
+ }
+ }
+
+ return result;
+}
\f
/* Given an rtx *P, if it is a sum containing an integer constant term,
return the location (type rtx *) of the pointer to that constant term.
register rtx z;
rtx y1 = y;
rtx *y2;
- int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p);
+ int (*addressp) PARAMS ((enum machine_mode, rtx)) =
+ (strictp ? strict_memory_address_p : memory_address_p);
+ unsigned int mode_sz = GET_MODE_SIZE (mode);
if (CONSTANT_ADDRESS_P (y))
return 1;
if (mode_dependent_address_p (y))
return 0;
+ /* ??? How much offset does an offsettable BLKmode reference need?
+ Clearly that depends on the situation in which it's being used.
+ However, the current situation in which we test 0xffffffff is
+ less than ideal. Caveat user. */
+ if (mode_sz == 0)
+ mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
+
/* If the expression contains a constant term,
see if it remains valid when max possible offset is added. */
int good;
y1 = *y2;
- *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1);
+ *y2 = plus_constant (*y2, mode_sz - 1);
/* Use QImode because an odd displacement may be automatically invalid
for any wider mode. But it should be valid for a single byte. */
good = (*addressp) (QImode, y);
return good;
}
- if (ycode == PRE_DEC || ycode == PRE_INC
- || ycode == POST_DEC || ycode == POST_INC)
+ if (GET_RTX_CLASS (ycode) == 'a')
return 0;
/* The offset added here is chosen as the maximum offset that
of the specified mode. We assume that if Y and Y+c are
valid addresses then so is Y+d for all 0<d<c. */
- z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1);
+ z = plus_constant_for_output (y, mode_sz - 1);
/* Use QImode because an odd displacement may be automatically invalid
for any wider mode. But it should be valid for a single byte. */
int
mode_dependent_address_p (addr)
- rtx addr;
+ rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
{
GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
return 0;
- win:
+ /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
+ win: ATTRIBUTE_UNUSED_LABEL
return 1;
}
addr = XEXP (op, 0);
GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
return 1;
- lose:
+ /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
+ lose: ATTRIBUTE_UNUSED_LABEL
return 0;
}
-/* Given an operand OP that is a valid memory reference
- which satisfies offsettable_memref_p,
- return a new memory reference whose address has been adjusted by OFFSET.
- OFFSET should be positive and less than the size of the object referenced.
-*/
+/* Given an operand OP that is a valid memory reference which
+ satisfies offsettable_memref_p, return a new memory reference whose
+ address has been adjusted by OFFSET. OFFSET should be positive and
+ less than the size of the object referenced. */
rtx
adj_offsettable_operand (op, offset)
if (CONSTANT_ADDRESS_P (y))
{
- new = gen_rtx (MEM, GET_MODE (op), plus_constant_for_output (y, offset));
- RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
+ new = gen_rtx_MEM (GET_MODE (op),
+ plus_constant_for_output (y, offset));
+ MEM_COPY_ATTRIBUTES (new, op);
return new;
}
}
}
- new = gen_rtx (MEM, GET_MODE (op), plus_constant_for_output (y, offset));
- RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
+ new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
+ MEM_COPY_ATTRIBUTES (new, op);
return new;
}
abort ();
}
\f
-#ifdef REGISTER_CONSTRAINTS
+/* Like extract_insn, but save insn extracted and don't extract again, when
+ called again for the same insn expecting that recog_data still contain the
+ valid information. This is used primary by gen_attr infrastructure that
+ often does extract insn again and again. */
+void
+extract_insn_cached (insn)
+ rtx insn;
+{
+ if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
+ return;
+ extract_insn (insn);
+ recog_data.insn = insn;
+}
+/* Do cached extract_insn, constrain_operand and complain about failures.
+ Used by insn_attrtab. */
+void
+extract_constrain_insn_cached (insn)
+ rtx insn;
+{
+ extract_insn_cached (insn);
+ if (which_alternative == -1
+ && !constrain_operands (reload_completed))
+ fatal_insn_not_found (insn);
+}
+/* Do cached constrain_operand and complain about failures. */
+int
+constrain_operands_cached (strict)
+ int strict;
+{
+ if (which_alternative == -1)
+ return constrain_operands (strict);
+ else
+ return 1;
+}
+\f
+/* Analyze INSN and fill in recog_data. */
+
+void
+extract_insn (insn)
+ rtx insn;
+{
+ int i;
+ int icode;
+ int noperands;
+ rtx body = PATTERN (insn);
+
+ recog_data.insn = NULL;
+ recog_data.n_operands = 0;
+ recog_data.n_alternatives = 0;
+ recog_data.n_dups = 0;
+ which_alternative = -1;
+
+ switch (GET_CODE (body))
+ {
+ case USE:
+ case CLOBBER:
+ case ASM_INPUT:
+ case ADDR_VEC:
+ case ADDR_DIFF_VEC:
+ return;
+
+ case SET:
+ if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
+ goto asm_insn;
+ else
+ goto normal_insn;
+ case PARALLEL:
+ if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
+ && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
+ || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
+ goto asm_insn;
+ else
+ goto normal_insn;
+ case ASM_OPERANDS:
+ asm_insn:
+ recog_data.n_operands = noperands = asm_noperands (body);
+ if (noperands >= 0)
+ {
+ /* This insn is an `asm' with operands. */
+
+ /* expand_asm_operands makes sure there aren't too many operands. */
+ if (noperands > MAX_RECOG_OPERANDS)
+ abort ();
+
+ /* Now get the operand values and constraints out of the insn. */
+ decode_asm_operands (body, recog_data.operand,
+ recog_data.operand_loc,
+ recog_data.constraints,
+ recog_data.operand_mode);
+ if (noperands > 0)
+ {
+ const char *p = recog_data.constraints[0];
+ recog_data.n_alternatives = 1;
+ while (*p)
+ recog_data.n_alternatives += (*p++ == ',');
+ }
+ break;
+ }
+ fatal_insn_not_found (insn);
+
+ default:
+ normal_insn:
+ /* Ordinary insn: recognize it, get the operands via insn_extract
+ and get the constraints. */
+
+ icode = recog_memoized (insn);
+ if (icode < 0)
+ fatal_insn_not_found (insn);
+
+ recog_data.n_operands = noperands = insn_data[icode].n_operands;
+ recog_data.n_alternatives = insn_data[icode].n_alternatives;
+ recog_data.n_dups = insn_data[icode].n_dups;
+
+ insn_extract (insn);
+
+ for (i = 0; i < noperands; i++)
+ {
+ recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
+ recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
+ /* VOIDmode match_operands gets mode from their real operand. */
+ if (recog_data.operand_mode[i] == VOIDmode)
+ recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
+ }
+ }
+ for (i = 0; i < noperands; i++)
+ recog_data.operand_type[i]
+ = (recog_data.constraints[i][0] == '=' ? OP_OUT
+ : recog_data.constraints[i][0] == '+' ? OP_INOUT
+ : OP_IN);
+
+ if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
+ abort ();
+}
+
+/* After calling extract_insn, you can use this function to extract some
+ information from the constraint strings into a more usable form.
+ The collected data is stored in recog_op_alt. */
+void
+preprocess_constraints ()
+{
+ int i;
+
+ memset (recog_op_alt, 0, sizeof recog_op_alt);
+ for (i = 0; i < recog_data.n_operands; i++)
+ {
+ int j;
+ struct operand_alternative *op_alt;
+ const char *p = recog_data.constraints[i];
+
+ op_alt = recog_op_alt[i];
+
+ for (j = 0; j < recog_data.n_alternatives; j++)
+ {
+ op_alt[j].class = NO_REGS;
+ op_alt[j].constraint = p;
+ op_alt[j].matches = -1;
+ op_alt[j].matched = -1;
+
+ if (*p == '\0' || *p == ',')
+ {
+ op_alt[j].anything_ok = 1;
+ continue;
+ }
+
+ for (;;)
+ {
+ char c = *p++;
+ if (c == '#')
+ do
+ c = *p++;
+ while (c != ',' && c != '\0');
+ if (c == ',' || c == '\0')
+ break;
+
+ switch (c)
+ {
+ case '=': case '+': case '*': case '%':
+ case 'E': case 'F': case 'G': case 'H':
+ case 's': case 'i': case 'n':
+ case 'I': case 'J': case 'K': case 'L':
+ case 'M': case 'N': case 'O': case 'P':
+ /* These don't say anything we care about. */
+ break;
+
+ case '?':
+ op_alt[j].reject += 6;
+ break;
+ case '!':
+ op_alt[j].reject += 600;
+ break;
+ case '&':
+ op_alt[j].earlyclobber = 1;
+ break;
+
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ op_alt[j].matches = c - '0';
+ recog_op_alt[op_alt[j].matches][j].matched = i;
+ break;
+
+ case 'm':
+ op_alt[j].memory_ok = 1;
+ break;
+ case '<':
+ op_alt[j].decmem_ok = 1;
+ break;
+ case '>':
+ op_alt[j].incmem_ok = 1;
+ break;
+ case 'V':
+ op_alt[j].nonoffmem_ok = 1;
+ break;
+ case 'o':
+ op_alt[j].offmem_ok = 1;
+ break;
+ case 'X':
+ op_alt[j].anything_ok = 1;
+ break;
+
+ case 'p':
+ op_alt[j].is_address = 1;
+ op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS];
+ break;
-/* Check the operands of an insn (found in recog_operands)
- against the insn's operand constraints (found via INSN_CODE_NUM)
+ case 'g': case 'r':
+ op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
+ break;
+
+ default:
+ op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
+ break;
+ }
+ }
+ }
+ }
+}
+
+/* Check the operands of an insn against the insn's operand constraints
and return 1 if they are valid.
+ The information about the insn's operands, constraints, operand modes
+ etc. is obtained from the global variables set up by extract_insn.
WHICH_ALTERNATIVE is set to a number which indicates which
alternative of constraints was matched: 0 for the first alternative,
};
int
-constrain_operands (insn_code_num, strict)
- int insn_code_num;
+constrain_operands (strict)
int strict;
{
- char *constraints[MAX_RECOG_OPERANDS];
+ const char *constraints[MAX_RECOG_OPERANDS];
int matching_operands[MAX_RECOG_OPERANDS];
- enum op_type {OP_IN, OP_OUT, OP_INOUT} op_types[MAX_RECOG_OPERANDS];
int earlyclobber[MAX_RECOG_OPERANDS];
register int c;
- int noperands = insn_n_operands[insn_code_num];
struct funny_match funny_match[MAX_RECOG_OPERANDS];
int funny_match_index;
- int nalternatives = insn_n_alternatives[insn_code_num];
- if (noperands == 0 || nalternatives == 0)
+ which_alternative = 0;
+ if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
return 1;
- for (c = 0; c < noperands; c++)
+ for (c = 0; c < recog_data.n_operands; c++)
{
- constraints[c] = insn_operand_constraint[insn_code_num][c];
+ constraints[c] = recog_data.constraints[c];
matching_operands[c] = -1;
- op_types[c] = OP_IN;
}
- which_alternative = 0;
-
- while (which_alternative < nalternatives)
+ do
{
register int opno;
int lose = 0;
funny_match_index = 0;
- for (opno = 0; opno < noperands; opno++)
+ for (opno = 0; opno < recog_data.n_operands; opno++)
{
- register rtx op = recog_operand[opno];
+ register rtx op = recog_data.operand[opno];
enum machine_mode mode = GET_MODE (op);
- register char *p = constraints[opno];
+ register const char *p = constraints[opno];
int offset = 0;
int win = 0;
int val;
earlyclobber[opno] = 0;
+ /* A unary operator may be accepted by the predicate, but it
+ is irrelevant for matching constraints. */
+ if (GET_RTX_CLASS (GET_CODE (op)) == '1')
+ op = XEXP (op, 0);
+
if (GET_CODE (op) == SUBREG)
{
if (GET_CODE (SUBREG_REG (op)) == REG
while (*p && (c = *p++) != ',')
switch (c)
{
- case '?':
- case '!':
- case '*':
- case '%':
+ case '?': case '!': case '*': case '%':
+ case '=': case '+':
break;
case '#':
p++;
break;
- case '=':
- op_types[opno] = OP_OUT;
- break;
-
- case '+':
- op_types[opno] = OP_INOUT;
- break;
-
case '&':
earlyclobber[opno] = 1;
break;
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+
/* This operand must be the same as a previous one.
This kind of constraint is used for instructions such
as add when they take only two operands.
if (strict < 0)
val = 1;
else
- val = operands_match_p (recog_operand[c - '0'],
- recog_operand[opno]);
+ {
+ rtx op1 = recog_data.operand[c - '0'];
+ rtx op2 = recog_data.operand[opno];
+
+ /* A unary operator may be accepted by the predicate,
+ but it is irrelevant for matching constraints. */
+ if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
+ op1 = XEXP (op1, 0);
+ if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
+ op2 = XEXP (op2, 0);
+
+ val = operands_match_p (op1, op2);
+ }
matching_operands[opno] = c - '0';
matching_operands[c - '0'] = opno;
case 'p':
/* p is used for address_operands. When we are called by
- gen_input_reload, no one will have checked that the
- address is strictly valid, i.e., that all pseudos
- requiring hard regs have gotten them. */
+ gen_reload, no one will have checked that the address is
+ strictly valid, i.e., that all pseudos requiring hard regs
+ have gotten them. */
if (strict <= 0
- || (strict_memory_address_p
- (insn_operand_mode[insn_code_num][opno], op)))
+ || (strict_memory_address_p (recog_data.operand_mode[opno],
+ op)))
win = 1;
break;
win = 1;
break;
- case 'r':
- if (strict < 0
- || (strict == 0
- && GET_CODE (op) == REG
- && REGNO (op) >= FIRST_PSEUDO_REGISTER)
- || (strict == 0 && GET_CODE (op) == SCRATCH)
- || (GET_CODE (op) == REG
- && ((GENERAL_REGS == ALL_REGS
- && REGNO (op) < FIRST_PSEUDO_REGISTER)
- || reg_fits_class_p (op, GENERAL_REGS,
- offset, mode))))
- win = 1;
- break;
-
case 'X':
- /* This is used for a MATCH_SCRATCH in the cases when we
- don't actually need anything. So anything goes any time. */
+ /* This is used for a MATCH_SCRATCH in the cases when
+ we don't actually need anything. So anything goes
+ any time. */
win = 1;
break;
break;
case 'E':
+#ifndef REAL_ARITHMETIC
/* Match any CONST_DOUBLE, but only if
we can examine the bits of it reliably. */
if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
|| HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
&& GET_MODE (op) != VOIDmode && ! flag_pretend_float)
break;
+#endif
if (GET_CODE (op) == CONST_DOUBLE)
win = 1;
break;
win = 1;
break;
-#ifdef EXTRA_CONSTRAINT
- case 'Q':
- case 'R':
- case 'S':
- case 'T':
- case 'U':
- if (EXTRA_CONSTRAINT (op, c))
- win = 1;
- break;
-#endif
-
case 'V':
if (GET_CODE (op) == MEM
- && ! offsettable_memref_p (op))
+ && ((strict > 0 && ! offsettable_memref_p (op))
+ || (strict < 0
+ && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
+ || (reload_in_progress
+ && !(GET_CODE (op) == REG
+ && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
win = 1;
break;
break;
default:
- if (strict < 0
- || (strict == 0
- && GET_CODE (op) == REG
- && REGNO (op) >= FIRST_PSEUDO_REGISTER)
- || (strict == 0 && GET_CODE (op) == SCRATCH)
- || (GET_CODE (op) == REG
- && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c),
- offset, mode)))
- win = 1;
+ {
+ enum reg_class class;
+
+ class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c));
+ if (class != NO_REGS)
+ {
+ if (strict < 0
+ || (strict == 0
+ && GET_CODE (op) == REG
+ && REGNO (op) >= FIRST_PSEUDO_REGISTER)
+ || (strict == 0 && GET_CODE (op) == SCRATCH)
+ || (GET_CODE (op) == REG
+ && reg_fits_class_p (op, class, offset, mode)))
+ win = 1;
+ }
+#ifdef EXTRA_CONSTRAINT
+ else if (EXTRA_CONSTRAINT (op, c))
+ win = 1;
+#endif
+ break;
+ }
}
constraints[opno] = p;
operand. */
if (strict > 0)
- for (eopno = 0; eopno < noperands; eopno++)
+ for (eopno = 0; eopno < recog_data.n_operands; eopno++)
/* Ignore earlyclobber operands now in memory,
because we would often report failure when we have
two memory operands, one of which was formerly a REG. */
if (earlyclobber[eopno]
- && GET_CODE (recog_operand[eopno]) == REG)
- for (opno = 0; opno < noperands; opno++)
- if ((GET_CODE (recog_operand[opno]) == MEM
- || op_types[opno] != OP_OUT)
+ && GET_CODE (recog_data.operand[eopno]) == REG)
+ for (opno = 0; opno < recog_data.n_operands; opno++)
+ if ((GET_CODE (recog_data.operand[opno]) == MEM
+ || recog_data.operand_type[opno] != OP_OUT)
&& opno != eopno
- /* Ignore things like match_operator operands. */
- && *constraints[opno] != 0
+ /* Ignore things like match_operator operands. */
+ && *recog_data.constraints[opno] != 0
&& ! (matching_operands[opno] == eopno
- && rtx_equal_p (recog_operand[opno],
- recog_operand[eopno]))
- && ! safe_from_earlyclobber (recog_operand[opno],
- recog_operand[eopno]))
+ && operands_match_p (recog_data.operand[opno],
+ recog_data.operand[eopno]))
+ && ! safe_from_earlyclobber (recog_data.operand[opno],
+ recog_data.operand[eopno]))
lose = 1;
if (! lose)
{
while (--funny_match_index >= 0)
{
- recog_operand[funny_match[funny_match_index].other]
- = recog_operand[funny_match[funny_match_index].this];
+ recog_data.operand[funny_match[funny_match_index].other]
+ = recog_data.operand[funny_match[funny_match_index].this];
}
return 1;
which_alternative++;
}
+ while (which_alternative < recog_data.n_alternatives);
+ which_alternative = -1;
/* If we are about to reject this, but we are not to test strictly,
try a very loose test. Only return failure if it fails also. */
if (strict == 0)
- return constrain_operands (insn_code_num, -1);
+ return constrain_operands (-1);
else
return 0;
}
/* Return 1 iff OPERAND (assumed to be a REG rtx)
- is a hard reg in class CLASS when its regno is offsetted by OFFSET
+ is a hard reg in class CLASS when its regno is offset by OFFSET
and changed to mode MODE.
If REG occupies multiple hard regs, all of them must be in CLASS. */
return 0;
}
+\f
+/* Split all insns in the function. If UPD_LIFE, update life info after. */
+
+void
+split_all_insns (upd_life)
+ int upd_life;
+{
+ sbitmap blocks;
+ int changed;
+ int i;
+
+ blocks = sbitmap_alloc (n_basic_blocks);
+ sbitmap_zero (blocks);
+ changed = 0;
+
+ for (i = n_basic_blocks - 1; i >= 0; --i)
+ {
+ basic_block bb = BASIC_BLOCK (i);
+ rtx insn, next;
-#endif /* REGISTER_CONSTRAINTS */
+ for (insn = bb->head; insn ; insn = next)
+ {
+ rtx set;
+
+ /* Can't use `next_real_insn' because that might go across
+ CODE_LABELS and short-out basic blocks. */
+ next = NEXT_INSN (insn);
+ if (! INSN_P (insn))
+ ;
+
+ /* Don't split no-op move insns. These should silently
+ disappear later in final. Splitting such insns would
+ break the code that handles REG_NO_CONFLICT blocks. */
+
+ else if ((set = single_set (insn)) != NULL
+ && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
+ {
+ /* Nops get in the way while scheduling, so delete them
+ now if register allocation has already been done. It
+ is too risky to try to do this before register
+ allocation, and there are unlikely to be very many
+ nops then anyways. */
+ if (reload_completed)
+ {
+ PUT_CODE (insn, NOTE);
+ NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+ NOTE_SOURCE_FILE (insn) = 0;
+ }
+ }
+ else
+ {
+ /* Split insns here to get max fine-grain parallelism. */
+ rtx first = PREV_INSN (insn);
+ rtx last = try_split (PATTERN (insn), insn, 1);
+
+ if (last != insn)
+ {
+ SET_BIT (blocks, i);
+ changed = 1;
+
+ /* try_split returns the NOTE that INSN became. */
+ PUT_CODE (insn, NOTE);
+ NOTE_SOURCE_FILE (insn) = 0;
+ NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+
+ /* ??? Coddle to md files that generate subregs in post-
+ reload splitters instead of computing the proper
+ hard register. */
+ if (reload_completed && first != last)
+ {
+ first = NEXT_INSN (first);
+ while (1)
+ {
+ if (INSN_P (first))
+ cleanup_subreg_operands (first);
+ if (first == last)
+ break;
+ first = NEXT_INSN (first);
+ }
+ }
+
+ if (insn == bb->end)
+ {
+ bb->end = last;
+ break;
+ }
+ }
+ }
+
+ if (insn == bb->end)
+ break;
+ }
+
+ /* ??? When we're called from just after reload, the CFG is in bad
+ shape, and we may have fallen off the end. This could be fixed
+ by having reload not try to delete unreachable code. Otherwise
+ assert we found the end insn. */
+ if (insn == NULL && upd_life)
+ abort ();
+ }
+
+ if (changed && upd_life)
+ {
+ compute_bb_for_insn (get_max_uid ());
+ count_or_remove_death_notes (blocks, 1);
+ update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
+ }
+
+ sbitmap_free (blocks);
+}
+\f
+#ifdef HAVE_peephole2
+struct peep2_insn_data
+{
+ rtx insn;
+ regset live_before;
+};
+
+static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
+static int peep2_current;
+
+/* A non-insn marker indicating the last insn of the block.
+ The live_before regset for this element is correct, indicating
+ global_live_at_end for the block. */
+#define PEEP2_EOB pc_rtx
+
+/* Return the Nth non-note insn after `current', or return NULL_RTX if it
+ does not exist. Used by the recognizer to find the next insn to match
+ in a multi-insn pattern. */
+
+rtx
+peep2_next_insn (n)
+ int n;
+{
+ if (n >= MAX_INSNS_PER_PEEP2 + 1)
+ abort ();
+
+ n += peep2_current;
+ if (n >= MAX_INSNS_PER_PEEP2 + 1)
+ n -= MAX_INSNS_PER_PEEP2 + 1;
+
+ if (peep2_insn_data[n].insn == PEEP2_EOB)
+ return NULL_RTX;
+ return peep2_insn_data[n].insn;
+}
+
+/* Return true if REGNO is dead before the Nth non-note insn
+ after `current'. */
+
+int
+peep2_regno_dead_p (ofs, regno)
+ int ofs;
+ int regno;
+{
+ if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+ abort ();
+
+ ofs += peep2_current;
+ if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+ ofs -= MAX_INSNS_PER_PEEP2 + 1;
+
+ if (peep2_insn_data[ofs].insn == NULL_RTX)
+ abort ();
+
+ return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
+}
+
+/* Similarly for a REG. */
+
+int
+peep2_reg_dead_p (ofs, reg)
+ int ofs;
+ rtx reg;
+{
+ int regno, n;
+
+ if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+ abort ();
+
+ ofs += peep2_current;
+ if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+ ofs -= MAX_INSNS_PER_PEEP2 + 1;
+
+ if (peep2_insn_data[ofs].insn == NULL_RTX)
+ abort ();
+
+ regno = REGNO (reg);
+ n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
+ while (--n >= 0)
+ if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
+ return 0;
+ return 1;
+}
+
+/* Try to find a hard register of mode MODE, matching the register class in
+ CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
+ remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
+ in which case the only condition is that the register must be available
+ before CURRENT_INSN.
+ Registers that already have bits set in REG_SET will not be considered.
+
+ If an appropriate register is available, it will be returned and the
+ corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
+ returned. */
+
+rtx
+peep2_find_free_register (from, to, class_str, mode, reg_set)
+ int from, to;
+ const char *class_str;
+ enum machine_mode mode;
+ HARD_REG_SET *reg_set;
+{
+ static int search_ofs;
+ enum reg_class class;
+ HARD_REG_SET live;
+ int i;
+
+ if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1)
+ abort ();
+
+ from += peep2_current;
+ if (from >= MAX_INSNS_PER_PEEP2 + 1)
+ from -= MAX_INSNS_PER_PEEP2 + 1;
+ to += peep2_current;
+ if (to >= MAX_INSNS_PER_PEEP2 + 1)
+ to -= MAX_INSNS_PER_PEEP2 + 1;
+
+ if (peep2_insn_data[from].insn == NULL_RTX)
+ abort ();
+ REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
+
+ while (from != to)
+ {
+ HARD_REG_SET this_live;
+
+ if (++from >= MAX_INSNS_PER_PEEP2 + 1)
+ from = 0;
+ if (peep2_insn_data[from].insn == NULL_RTX)
+ abort ();
+ REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
+ IOR_HARD_REG_SET (live, this_live);
+ }
+
+ class = (class_str[0] == 'r' ? GENERAL_REGS
+ : REG_CLASS_FROM_LETTER (class_str[0]));
+
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ {
+ int raw_regno, regno, success, j;
+
+ /* Distribute the free registers as much as possible. */
+ raw_regno = search_ofs + i;
+ if (raw_regno >= FIRST_PSEUDO_REGISTER)
+ raw_regno -= FIRST_PSEUDO_REGISTER;
+#ifdef REG_ALLOC_ORDER
+ regno = reg_alloc_order[raw_regno];
+#else
+ regno = raw_regno;
+#endif
+
+ /* Don't allocate fixed registers. */
+ if (fixed_regs[regno])
+ continue;
+ /* Make sure the register is of the right class. */
+ if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno))
+ continue;
+ /* And can support the mode we need. */
+ if (! HARD_REGNO_MODE_OK (regno, mode))
+ continue;
+ /* And that we don't create an extra save/restore. */
+ if (! call_used_regs[regno] && ! regs_ever_live[regno])
+ continue;
+ /* And we don't clobber traceback for noreturn functions. */
+ if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
+ && (! reload_completed || frame_pointer_needed))
+ continue;
+
+ success = 1;
+ for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
+ {
+ if (TEST_HARD_REG_BIT (*reg_set, regno + j)
+ || TEST_HARD_REG_BIT (live, regno + j))
+ {
+ success = 0;
+ break;
+ }
+ }
+ if (success)
+ {
+ for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
+ SET_HARD_REG_BIT (*reg_set, regno + j);
+
+ /* Start the next search with the next register. */
+ if (++raw_regno >= FIRST_PSEUDO_REGISTER)
+ raw_regno = 0;
+ search_ofs = raw_regno;
+
+ return gen_rtx_REG (mode, regno);
+ }
+ }
+
+ search_ofs = 0;
+ return NULL_RTX;
+}
+
+/* Perform the peephole2 optimization pass. */
+
+void
+peephole2_optimize (dump_file)
+ FILE *dump_file ATTRIBUTE_UNUSED;
+{
+ regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
+ rtx insn, prev;
+ regset live;
+ int i, b;
+#ifdef HAVE_conditional_execution
+ sbitmap blocks;
+ int changed;
+#endif
+
+ /* Initialize the regsets we're going to use. */
+ for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+ peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]);
+ live = INITIALIZE_REG_SET (rs_heads[i]);
+
+#ifdef HAVE_conditional_execution
+ blocks = sbitmap_alloc (n_basic_blocks);
+ sbitmap_zero (blocks);
+ changed = 0;
+#else
+ count_or_remove_death_notes (NULL, 1);
+#endif
+
+ for (b = n_basic_blocks - 1; b >= 0; --b)
+ {
+ basic_block bb = BASIC_BLOCK (b);
+ struct propagate_block_info *pbi;
+
+ /* Indicate that all slots except the last holds invalid data. */
+ for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
+ peep2_insn_data[i].insn = NULL_RTX;
+
+ /* Indicate that the last slot contains live_after data. */
+ peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
+ peep2_current = MAX_INSNS_PER_PEEP2;
+
+ /* Start up propagation. */
+ COPY_REG_SET (live, bb->global_live_at_end);
+ COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
+
+#ifdef HAVE_conditional_execution
+ pbi = init_propagate_block_info (bb, live, NULL, 0);
+#else
+ pbi = init_propagate_block_info (bb, live, NULL, PROP_DEATH_NOTES);
+#endif
+
+ for (insn = bb->end; ; insn = prev)
+ {
+ prev = PREV_INSN (insn);
+ if (INSN_P (insn))
+ {
+ rtx try;
+ int match_len;
+
+ /* Record this insn. */
+ if (--peep2_current < 0)
+ peep2_current = MAX_INSNS_PER_PEEP2;
+ peep2_insn_data[peep2_current].insn = insn;
+ propagate_one_insn (pbi, insn);
+ COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
+
+ /* Match the peephole. */
+ try = peephole2_insns (PATTERN (insn), insn, &match_len);
+ if (try != NULL)
+ {
+ i = match_len + peep2_current;
+ if (i >= MAX_INSNS_PER_PEEP2 + 1)
+ i -= MAX_INSNS_PER_PEEP2 + 1;
+
+ /* Replace the old sequence with the new. */
+ flow_delete_insn_chain (insn, peep2_insn_data[i].insn);
+ try = emit_insn_after (try, prev);
+
+ /* Adjust the basic block boundaries. */
+ if (peep2_insn_data[i].insn == bb->end)
+ bb->end = try;
+ if (insn == bb->head)
+ bb->head = NEXT_INSN (prev);
+
+#ifdef HAVE_conditional_execution
+ /* With conditional execution, we cannot back up the
+ live information so easily, since the conditional
+ death data structures are not so self-contained.
+ So record that we've made a modification to this
+ block and update life information at the end. */
+ SET_BIT (blocks, b);
+ changed = 1;
+
+ for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+ peep2_insn_data[i].insn = NULL_RTX;
+ peep2_insn_data[peep2_current].insn = PEEP2_EOB;
+#else
+ /* Back up lifetime information past the end of the
+ newly created sequence. */
+ if (++i >= MAX_INSNS_PER_PEEP2 + 1)
+ i = 0;
+ COPY_REG_SET (live, peep2_insn_data[i].live_before);
+
+ /* Update life information for the new sequence. */
+ do
+ {
+ if (INSN_P (try))
+ {
+ if (--i < 0)
+ i = MAX_INSNS_PER_PEEP2;
+ peep2_insn_data[i].insn = try;
+ propagate_one_insn (pbi, try);
+ COPY_REG_SET (peep2_insn_data[i].live_before, live);
+ }
+ try = PREV_INSN (try);
+ }
+ while (try != prev);
+
+ /* ??? Should verify that LIVE now matches what we
+ had before the new sequence. */
+
+ peep2_current = i;
+#endif
+ }
+ }
+
+ if (insn == bb->head)
+ break;
+ }
+
+ free_propagate_block_info (pbi);
+ }
+
+ for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+ FREE_REG_SET (peep2_insn_data[i].live_before);
+ FREE_REG_SET (live);
+
+#ifdef HAVE_conditional_execution
+ count_or_remove_death_notes (blocks, 1);
+ update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
+ sbitmap_free (blocks);
+#endif
+}
+#endif /* HAVE_peephole2 */