In the process of building the interference graph web parts are
connected together, if they have common instructions and reference the
same register. That way live ranges are build (by connecting defs and
- uses) and implicitely complete webs (by connecting web parts in common
+ uses) and implicitly complete webs (by connecting web parts in common
uses). */
struct web_part
{
was illegal for hardregs in CLASS_CANNOT_CHANGE_MODE. */
unsigned int mode_changed:1;
+ /* Nonzero if some references of this web, where in subreg context,
+ but the actual subreg is already stripped (i.e. we don't know the
+ outer mode of the actual reference). */
+ unsigned int subreg_stripped:1;
+
/* Nonzero, when this web stems from the last pass of the allocator,
and all info is still valid (i.e. it wasn't spilled). */
unsigned int old_web:1;
/* Number of usable colors in usable_regs. */
int num_freedom;
- /* After successfull coloring the graph each web gets a new reg rtx,
+ /* After successful coloring the graph each web gets a new reg rtx,
with which the original uses and defs are replaced. This is it. */
rtx reg_rtx;
/* This is the bitmap of all (even partly) conflicting super webs.
If bit I*num_webs+J or J*num_webs+I is set, then I and J (both being
super web indices) conflict, maybe only partially. Note the
- assymetry. */
+ asymmetry. */
extern sbitmap sup_igraph;
/* After the first pass, and when interference region spilling is
which backward reach the end of B. */
extern bitmap *live_at_end;
-/* One pass is: collecting registers refs, buiding I-graph, spilling.
+/* One pass is: collecting registers refs, building I-graph, spilling.
And this is how often we already ran that for the current function. */
extern int ra_pass;
/* The largest DF_REF_ID of defs resp. uses, as it was in the
last pass. In the first pass this is zero. Used to distinguish new
- from old refrences. */
+ from old references. */
extern unsigned int last_def_id;
extern unsigned int last_use_id;
/* For each class C the count of hardregs in usable_regs[C]. */
extern unsigned int num_free_regs[N_REG_CLASSES];
/* For each mode M the hardregs, which are MODE_OK for M, and have
- enough space behind them to hold an M value. Additinally
+ enough space behind them to hold an M value. Additionally
if reg R is OK for mode M, but it needs two hardregs, then R+1 will
also be set here, even if R+1 itself is not OK for M. I.e. this
represent the possible resources which could be taken away be a value
in mode M. */
extern HARD_REG_SET hardregs_for_mode[NUM_MACHINE_MODES];
+/* The set of hardregs, for which _any_ mode change is invalid. */
+extern HARD_REG_SET invalid_mode_change_regs;
/* For 0 <= I <= 255, the number of bits set in I. Used to calculate
the number of set bits in a HARD_REG_SET. */
extern unsigned char byte2bitcount[256];
extern int flag_ra_merge_spill_costs;
/* Nonzero if we want to spill at every use, instead of at deaths,
- or intereference region borders. */
+ or interference region borders. */
extern int flag_ra_spill_every_use;
/* Nonzero to output all notes in the debug dumps. */