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[pf3gnuchains/gcc-fork.git] / gcc / ira-emit.c

diff --git a/gcc/ira-emit.c b/gcc/ira-emit.c
index 4b5068e..3dcd324 100644 (file)
--- a/gcc/ira-emit.c
+++ b/gcc/ira-emit.c
@@ -229,7 +229,7 @@ free_move_list (move_t head)
     }
 }
 
-/* Return TRUE if the the move list LIST1 and LIST2 are equal (two
+/* Return TRUE if the move list LIST1 and LIST2 are equal (two
    moves are equal if they involve the same allocnos).  */
 static bool
 eq_move_lists_p (move_t list1, move_t list2)
@@ -438,6 +438,7 @@ setup_entered_from_non_parent_p (void)
   unsigned int i;
   loop_p loop;
 
+  ira_assert (current_loops != NULL);
   FOR_EACH_VEC_ELT (loop_p, ira_loops.larray, i, loop)
     if (ira_loop_nodes[i].regno_allocno_map != NULL)
       ira_loop_nodes[i].entered_from_non_parent_p
@@ -565,7 +566,8 @@ change_loop (ira_loop_tree_node_t node)
 
   if (node != ira_loop_tree_root)
     {
-
+      ira_assert (current_loops != NULL);
+      
       if (node->bb != NULL)
        {
          FOR_BB_INSNS (node->bb, insn)
@@ -580,7 +582,7 @@ change_loop (ira_loop_tree_node_t node)
       if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL)
        fprintf (ira_dump_file,
                 "      Changing RTL for loop %d (header bb%d)\n",
-                node->loop->num, node->loop->header->index);
+                node->loop_num, node->loop->header->index);
 
       parent = ira_curr_loop_tree_node->parent;
       map = parent->regno_allocno_map;
@@ -900,8 +902,8 @@ modify_move_list (move_t list)
 static rtx
 emit_move_list (move_t list, int freq)
 {
-  int cost;
-  rtx result, insn;
+  int cost, regno;
+  rtx result, insn, set, to;
   enum machine_mode mode;
   enum reg_class aclass;
 
@@ -913,12 +915,34 @@ emit_move_list (move_t list, int freq)
                      allocno_emit_reg (list->from));
       list->insn = get_insns ();
       end_sequence ();
-      /* The reload needs to have set up insn codes.  If the reload
-        sets up insn codes by itself, it may fail because insns will
-        have hard registers instead of pseudos and there may be no
-        machine insn with given hard registers.  */
       for (insn = list->insn; insn != NULL_RTX; insn = NEXT_INSN (insn))
-       recog_memoized (insn);
+       {
+         /* The reload needs to have set up insn codes.  If the
+            reload sets up insn codes by itself, it may fail because
+            insns will have hard registers instead of pseudos and
+            there may be no machine insn with given hard
+            registers.  */
+         recog_memoized (insn);
+         /* Add insn to equiv init insn list if it is necessary.
+            Otherwise reload will not remove this insn if it decides
+            to use the equivalence.  */
+         if ((set = single_set (insn)) != NULL_RTX)
+           {
+             to = SET_DEST (set);
+             if (GET_CODE (to) == SUBREG)
+               to = SUBREG_REG (to);
+             ira_assert (REG_P (to));
+             regno = REGNO (to);
+             if (regno >= ira_reg_equiv_len
+                 || (! ira_reg_equiv_invariant_p[regno]
+                     && ira_reg_equiv_const[regno] == NULL_RTX))
+               continue; /* regno has no equivalence.  */
+             ira_assert ((int) VEC_length (reg_equivs_t, reg_equivs)
+                         >= ira_reg_equiv_len);
+             reg_equiv_init (regno)
+               = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno));
+           }
+       }
       emit_insn (list->insn);
       mode = ALLOCNO_MODE (list->to);
       aclass = ALLOCNO_CLASS (list->to);