int alt_fail = 0;
int alt_cost = 0, op_cost_add;
+ if (!recog_data.alternative_enabled_p[alt])
+ {
+ for (i = 0; i < recog_data.n_operands; i++)
+ constraints[i] = skip_alternative (constraints[i]);
+
+ continue;
+ }
+
for (i = 0; i < n_ops; i++)
{
unsigned char c;
continue;
}
}
-
+
/* Scan all the constraint letters. See if the operand
matches any of the constraints. Collect the valid
register classes and see if this operand accepts
{
ira_allocno_t a;
rtx op = ops[i];
-
+
if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
continue;
a = ira_curr_regno_allocno_map [REGNO (op)];
if (! TEST_HARD_REG_BIT (reg_class_contents[rclass],
regno + nr))
break;
-
+
if (nr == (unsigned) hard_regno_nregs[regno][mode])
op_costs[i]->cost[k] = -frequency;
}
{
ira_allocno_t a;
ira_allocno_iterator ai;
-
+
pref = pref_buffer;
FOR_EACH_ALLOCNO (a, ai)
pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a));
if (regno_cover_class[i] == NO_REGS)
best = NO_REGS;
else
- {
+ {
/* Finding best class which is subset of the common
class. */
best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
pref[a_num] = best;
}
}
-
+
if (internal_flag_ira_verbose > 4 && dump_file)
{
if (allocno_p)
int i, j, n, regno, num;
int *reg_costs;
enum reg_class cover_class, rclass;
- enum machine_mode mode;
ira_allocno_t a;
ira_allocno_iterator ai;
FOR_EACH_ALLOCNO (a, ai)
{
i = ALLOCNO_NUM (a);
- mode = ALLOCNO_MODE (a);
cover_class = regno_cover_class[ALLOCNO_REGNO (a)];
ira_assert (pref[i] == NO_REGS || cover_class != NO_REGS);
ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost;
}
if (min_cost != INT_MAX)
ALLOCNO_COVER_CLASS_COST (a) = min_cost;
+
+ /* Some targets allow pseudos to be allocated to unaligned
+ sequences of hard registers. However, selecting an unaligned
+ sequence can unnecessarily restrict later allocations. So
+ increase the cost of unaligned hard regs to encourage the use
+ of aligned hard regs. */
+ {
+ int nregs, index;
+
+ if ((nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)]) > 1)
+ {
+ ira_allocate_and_set_costs
+ (&ALLOCNO_HARD_REG_COSTS (a), cover_class,
+ ALLOCNO_COVER_CLASS_COST (a));
+ reg_costs = ALLOCNO_HARD_REG_COSTS (a);
+ for (j = n - 1; j >= 0; j--)
+ {
+ if (j % nregs != 0)
+ {
+ regno = ira_non_ordered_class_hard_regs[cover_class][j];
+ index = ira_class_hard_reg_index[cover_class][regno];
+ ira_assert (index != -1);
+ reg_costs[index] += ALLOCNO_FREQ (a);
+ }
+ }
+ }
+ }
}
}