-fno-for-scope -fno-gnu-keywords -fguiding-decls -fhandle-signatures
-fhonor-std -fhuge-objects -fno-implicit-templates -finit-priority
-fno-implement-inlines -fname-mangling-version-@var{n} -fno-default-inline
--foperator-names -fno-optional-diags -frepo -fstrict-prototype
+-foperator-names -fno-optional-diags -fpermissive -frepo -fstrict-prototype
-fsquangle -ftemplate-depth-@var{n} -fthis-is-variable -fvtable-thunks
--nostdinc++ -Wctor-dtor-privacy -Weffc++ -Wno-non-template-friend
+-nostdinc++ -Wctor-dtor-privacy -Wno-deprecated -Weffc++
+-Wno-non-template-friend
-Wnon-virtual-dtor -Wold-style-cast -Woverloaded-virtual
-Wno-pmf-conversions -Wreorder -Wsign-promo -Wsynth
@end smallexample
-fdelayed-branch -fexpensive-optimizations
-ffast-math -ffloat-store -fforce-addr -fforce-mem
-fdata-sections -ffunction-sections -fgcse
--finline-functions -fkeep-inline-functions
+-finline-functions -finline-limit-@var{n} -fkeep-inline-functions
-fno-default-inline -fno-defer-pop -fno-function-cse
-fno-inline -fno-peephole -fomit-frame-pointer -fregmove
-frerun-cse-after-loop -frerun-loop-opt -fschedule-insns
@emph{M680x0 Options}
-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040
-m68060 -mcpu32 -m5200 -m68881 -mbitfield -mc68000 -mc68020
--mfpa -mnobitfield -mrtd -mshort -msoft-float
+-mfpa -mnobitfield -mrtd -mshort -msoft-float -mpcrel
-malign-int
@emph{VAX Options}
-mbsd -mxopen -mno-symrename
-mabort-on-noreturn
-mno-sched-prolog
+-mnop-fun-dllimport -mno-nop-fun-dllimport
@emph{Thumb Options}
-mtpcs-frame -mno-tpcs-frame
-mlittle-endian -mbig-endian
-mthumb-interwork -mno-thumb-interwork
-mstructure-size-boundary=
+-mnop-fun-dllimport -mno-nop-fun-dllimport
+-mcallee-super-interworking -mno-callee-super-interworking
+-mcaller-super-interworking -mno-caller-super-interworking
@emph{MN10200 Options}
-mrelax
-mno-wide-multiply -mrtd -malign-double
-mreg-alloc=@var{list} -mregparm=@var{num}
-malign-jumps=@var{num} -malign-loops=@var{num}
--malign-functions=@var{num}
+-malign-functions=@var{num} -mpreferred-stack-boundary=@var{num}
@emph{HPPA Options}
+-march=@var{architecture type}
-mbig-switch -mdisable-fpregs -mdisable-indexing
-mfast-indirect-calls -mgas -mjump-in-delay
-mlong-load-store -mno-big-switch -mno-disable-fpregs
-mno-jump-in-delay -mno-long-load-store
-mno-portable-runtime -mno-soft-float -mno-space
-mno-space-regs -msoft-float -mpa-risc-1-0
--mpa-risc-1-1 -mportable-runtime
--mschedule=@var{list} -mspace -mspace-regs
+-mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime
+-mschedule=@var{cpu type} -mspace -mspace-regs
@emph{Intel 960 Options}
-m@var{cpu type} -masm-compat -mclean-linkage
-mmangle-cpu -mcpu=@var{cpu} -mtext=@var{text section}
-mdata=@var{data section} -mrodata=@var{readonly data section}
+@emph{TMS320C3x/C4x Options}
+-mcpu=@var{cpu} -mbig -msmall -mregparm -mmemparm
+-mfast-fix -mmpyi -mbk -mti -mdp-isr-reload
+-mrpts=@var{count} -mrptb -mdb -mloop-unsigned
+-mparallel-insns -mparallel-mpy -mpreserve-float
+
@emph{V850 Options}
-mlong-calls -mno-long-calls -mep -mno-ep
-mprolog-function -mno-prolog-function -mspace
that the standard library headers do not obey all of these guidelines;
you can use @samp{grep -v} to filter out those warnings.
+@item -Wno-deprecated (C++ only)
+Do not warn about usage of deprecated features. @xref{Deprecated Features}.
+
@item -Wno-non-template-friend (C++ only)
Disable warnings when non-templatized friend functions are declared
within a template. With the advent of explicit template specification
@item D
Dump all macro definitions, at the end of preprocessing, in addition to
normal output.
-@item y
-Dump debugging information during parsing, to standard error.
@item r
Dump after RTL generation, to @file{@var{file}.rtl}.
-@item x
-Just generate RTL for a function instead of compiling it. Usually used
-with @samp{r}.
@item j
Dump after first jump optimization, to @file{@var{file}.jump}.
-@item s
-Dump after CSE (including the jump optimization that sometimes
-follows CSE), to @file{@var{file}.cse}.
@item F
Dump after purging ADDRESSOF, to @file{@var{file}.addressof}.
@item f
@item t
Dump after the second CSE pass (including the jump optimization that
sometimes follows CSE), to @file{@var{file}.cse2}.
-@item x
-Just generate RTL for a function instead of compiling it. Usually used
-with @samp{r}.
@item a
Produce all the dumps listed above.
@item m
standard error.
@item p
Annotate the assembler output with a comment indicating which
-pattern and alternative was used.
+pattern and alternative was used. The length of each instruction is
+also printed.
+@item x
+Just generate RTL for a function instead of compiling it. Usually used
+with @samp{r}.
@item y
Dump debugging information during parsing, to standard error.
@item A
declared @code{static}, then the function is normally not output as
assembler code in its own right.
+@item -finline-limit-@var{n}
+By default, gcc limits the size of functions that can be inlined. This flag
+allows the control of this limit for functions that are explicitly marked as
+inline (ie marked with the inline keyword or defined within the class
+definition in c++). @var{n} is the size of functions that can be inlined in
+number of pseudo instructions (not counting parameter handling). The default
+value of n is 10000. Increasing this value can result in more inlined code at
+the cost of compilation time and memory consumption. Decreasing usually makes
+the compilation faster and less code will be inlined (which presumably
+means slower programs). This option is particularly useful for programs that
+use inlining heavily such as those based on recursive templates with c++.
+
+@emph{Note:} pseudo instruction represents, in this particular context, an
+abstract measurement of function's size. In no way, it represents a count
+of assembly instructions and as such its exact meaning might change from one
+release to an another.
+
@item -fkeep-inline-functions
Even if all calls to a given function are integrated, and the function
is declared @code{static}, nevertheless output a separate run-time
* H8/300 Options::
* SH Options::
* System V Options::
+* TMS320C3x/C4x Options::
* V850 Options::
* ARC Options::
* NS32K Options::
align structures containing the above types differently than
most published application binary interface specifications for the m68k.
+@item -mpcrel
+Use the pc-relative addressing mode of the 68000 directly, instead of
+using a global offset table. At present, this option implies -fpic,
+allowing at most a 16-bit offset for pc-relative addressing. -fPIC is
+not presently supported with -mpcrel, though this could be supported for
+68020 and higher processors.
+
@end table
@node VAX Options
compiler is built for cross-compilation.
@item -mcpu=<name>
-@itemx -mtune=<name>
@kindex -mcpu=
-@kindex -mtune=
This specifies the name of the target ARM processor. GCC uses this name
to determine what kind of instructions it can use when generating
assembly code. Permissable names are: arm2, arm250, arm3, arm6, arm60,
arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi,
arm70, arm700, arm700i, arm710, arm710c, arm7100, arm7500, arm7500fe,
arm7tdmi, arm8, strongarm, strongarm110, strongarm1100, arm8, arm810,
-arm9, arm9tdmi. @samp{-mtune=} is a synonym for @samp{-mcpue=} to
-support older versions of GCC.
+arm9, arm920, arm920t, arm9tdmi.
+
+@itemx -mtune=<name>
+@kindex -mtune=
+This option is very similar to the @samp{-mcpu=} option, except that
+instead of specifying the actual target processor type, and hence
+restricting which instructions can be used, it specifies that GCC should
+tune the performance of the code as if the target were of the type
+specified in this option, but still choosing the instructions that it
+will generate based on the cpu specified by a @samp{-mcpu=} option.
+For some arm implementations better performance can be obtained by using
+this option.
@item -march=<name>
@kindex -march=
name to determine what kind of instructions it can use when generating
assembly code. This option can be used in conjunction with or instead
of the @samp{-mcpu=} option. Permissable names are: armv2, armv2a,
-armv3, armv3m, armv4, armv4t
+armv3, armv3m, armv4, armv4t, armv5.
@item -mfpe=<number>
@itemx -mfp=<number>
Generate a call to the function abort at the end of a noreturn function.
It will be executed if the function tries to return.
+@item -mnop-fun-dllimport
+@kindex -mnop-fun-dllimport
+Disable the support for the @emph{dllimport} attribute.
+
@end table
@node Thumb Options
using structures or unions. Programmers are encouraged to use the 32
value as future versions of the toolchain may default to this value.
+@item -mnop-fun-dllimport
+@kindex -mnop-fun-dllimport
+Disable the support for the @emph{dllimport} attribute.
+
+@item -mcallee-super-interworking
+@kindex -mcallee-super-interworking
+Gives all externally visible functions in the file being compiled an ARM
+instruction set header which switches to Thumb mode before executing the
+rest of the function. This allows these functions to be called from
+non-interworking code.
+
+@item -mcaller-super-interworking
+@kindex -mcaller-super-interworking
+Allows calls via function pointers (including virtual functions) to
+execute correctly regardless of whether the target code has been
+compiled for interworking or not. There is a small overhead in the cost
+of executing a funciton pointer if this option is enabled.
+
@end table
@node MN10200 Options
@item -mcpu=@var{cpu type}
Assume the defaults for the machine type @var{cpu type} when scheduling
instructions. The choices for @var{cpu type} are @samp{r2000}, @samp{r3000},
-@samp{r4000}, @samp{r4400}, @samp{r4600}, and @samp{r6000}. While picking a
-specific @var{cpu type} will schedule things appropriately for that
-particular chip, the compiler will not generate any code that does not
-meet level 1 of the MIPS ISA (instruction set architecture) without
-the @samp{-mips2} or @samp{-mips3} switches being used.
+@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
+@samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000}, @samp{r8000},
+and @samp{orion}. Additionally, the @samp{r2000}, @samp{r3000},
+@samp{r4000}, @samp{r5000}, and @samp{r6000} can be abbreviated as
+@samp{r2k} (or @samp{r2K}), @samp{r3k}, etc. While picking a specific
+@var{cpu type} will schedule things appropriately for that particular
+chip, the compiler will not generate any code that does not meet level 1
+of the MIPS ISA (instruction set architecture) without a @samp{-mipsX}
+or @samp{-mabi} switch being used.
@item -mips1
Issue instructions from level 1 of the MIPS ISA. This is the default.
@samp{r4000} is the default @var{cpu type} at this ISA level.
@item -mips4
-Issue instructions from level 4 of the MIPS ISA. @samp{r8000} is the
-default @var{cpu type} at this ISA level.
+Issue instructions from level 4 of the MIPS ISA (conditional move,
+prefetch, enhanced FPU instructions). @samp{r8000} is the default
+@var{cpu type} at this ISA level.
@item -mfp32
Assume that 32 32-bit floating point registers are available. This is
the smaller of the width of longs or the width of general purpose
registers (which in turn depends on the ISA).
-@itemx -mabi=32
+@item -mabi=32
+@itemx -mabi=o64
@itemx -mabi=n32
@itemx -mabi=64
@itemx -mabi=eabi
-Generate code for the indicated ABI.
+Generate code for the indicated ABI. The default instruction level is
+@samp{-mips1} for @samp{32}, @samp{-mips3} for @samp{n32}, and
+@samp{-mips4} otherwise. Conversely, with @samp{-mips1} or
+@samp{-mips2}, the default ABI is @samp{32}; otherwise, the default ABI
+is @samp{64}.
@item -mmips-as
Generate code for the MIPS assembler, and invoke @file{mips-tfile} to
Turns on @samp{-msingle-float}, @samp{-mmad}, and, at least for now,
@samp{-mcpu=r4650}.
+@item -mips16
+@itemx -mno-mips16
+Enable 16-bit instructions.
+
+@item -mentry
+Use the entry and exit pseudo ops. This option can only be used with
+@samp{-mips16}.
+
@item -EL
Compile code for the processor in little endian mode.
The requisite libraries are assumed to exist.
@table @code
@item -mcpu=@var{cpu type}
Assume the defaults for the machine type @var{cpu type} when scheduling
-instructions. The choices for @var{cpu type} are: @samp{i386},
-@samp{i486}, @samp{i586} (@samp{pentium}), @samp{pentium}, @samp{i686}
-(@samp{pentiumpro}) and @samp{pentiumpro}. While picking a specific
-@var{cpu type} will schedule things appropriately for that particular
-chip, the compiler will not generate any code that does not run on the
-i386 without the @samp{-march=@var{cpu type}} option being used.
+instructions. The choices for @var{cpu type} are:
+
+@multitable @columnfractions .20 .20 .20 .20
+@item @samp{i386} @tab @samp{i486} @tab @samp{i586} @tab @samp{i686}
+@item @samp{pentium} @tab @samp{pentiumpro} @tab @samp{k6}
+@end multitable
+
+While picking a specific @var{cpu type} will schedule things appropriately
+for that particular chip, the compiler will not generate any code that
+does not run on the i386 without the @samp{-march=@var{cpu type}} option
+being used. @samp{i586} is equivalent to @samp{pentium} and @samp{i686}
+is equivalent to @samp{pentiumpro}. @samp{k6} is the AMD chip as
+opposed to the Intel ones.
@item -march=@var{cpu type}
Generate instructions for the machine type @var{cpu type}. The choices
-for @var{cpu type} are: @samp{i386}, @samp{i486}, @samp{pentium}, and
-@samp{pentiumpro}. Specifying @samp{-march=@var{cpu type}} implies
-@samp{-mcpu=@var{cpu type}}.
+for @var{cpu type} are the same as for @samp{-mcpu}. Moreover,
+specifying @samp{-march=@var{cpu type}} implies @samp{-mcpu=@var{cpu type}}.
@item -m386
@itemx -m486
@itemx -mpentium
@itemx -mpentiumpro
Synonyms for -mcpu=i386, -mcpu=i486, -mcpu=pentium, and -mcpu=pentiumpro
-respectively.
+respectively. These synonyms are deprecated.
@item -mieee-fp
@itemx -mno-ieee-fp
Align the start of functions to a 2 raised to @var{num} byte boundary.
If @samp{-malign-functions} is not specified, the default is 2 if optimizing
for a 386, and 4 if optimizing for a 486.
+
+@item -mpreferred-stack-boundary=@var{num}
+Attempt to keep the stack boundary aligned to a 2 raised to @var{num}
+byte boundary. If @samp{-mpreferred-stack-boundary} is not specified,
+the default is 4 (16 bytes or 128 bits).
+
+The stack is required to be aligned on a 4 byte boundary. On Pentium
+and PentiumPro, @code{double} and @code{long double} values should be
+aligned to an 8 byte boundary (see @samp{-malign-double}) or suffer
+significant run time performance penalties. On Pentium III, the
+Streaming SIMD Extention (SSE) data type @code{__m128} suffers similar
+penalties if it is not 16 byte aligned.
+
+To ensure proper alignment of this values on the stack, the stack boundary
+must be as aligned as that required by any value stored on the stack.
+Further, every function must be generated such that it keeps the stack
+aligned. Thus calling a function compiled with a higher preferred
+stack boundary from a function compiled with a lower preferred stack
+boundary will most likely misalign the stack. It is recommended that
+libraries that use callbacks always use the default setting.
+
+This extra alignment does consume extra stack space. Code that is sensitive
+to stack space usage, such as embedded systems and operating system kernels,
+may want to reduce the preferred alignment to
+@samp{-mpreferred-stack-boundary=2}.
@end table
@node HPPA Options
These @samp{-m} options are defined for the HPPA family of computers:
@table @code
-@item -mpa-risc-1-0
-Generate code for a PA 1.0 processor.
+@item -march=@var{architecture type}
+Generate code for the specified architecture. The choices for
+@var{architecture type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
+1.1, and @samp{2.0} for PA 2.0 processors. Refer to
+@file{/usr/lib/sched.models} on an HP-UX system to determine the proper
+architecture option for your machine. Code compiled for lower numbered
+architectures will run on higher numbered architectures, but not the
+other way around.
+
+PA 2.0 support currently requires gas snapshot 19990413 or later. The
+next release of binutils (current is 2.9.1) will probably contain PA 2.0
+support.
-@item -mpa-risc-1-1
-Generate code for a PA 1.1 processor.
+@item -mpa-risc-1-0
+@itemx -mpa-risc-1-1
+@itemx -mpa-risc-2-0
+Synonyms for -march=1.0, -march=1.1, and -march=2.0 respectively.
@item -mbig-switch
Generate code suitable for big switch tables. Use this option only if
@item -mc300
Produce code for a C300 Clipper processor. This is the default.
-@itemx -mc400
+@item -mc400
Produce code for a C400 Clipper processor i.e. use floating point
registers f8..f15.
@end table
@c the generic assembler that comes with Solaris takes just -Ym.
@end table
+@node TMS320C3x/C4x Options
+@subsection TMS320C3x/C4x Options
+@cindex TMS320C3x/C4x Options
+
+These @samp{-m} options are defined for TMS320C3x/C4x implementations:
+
+@table @code
+
+@item -mcpu=@var{cpu_type}
+Set the instruction set, register set, and instruction scheduling
+parameters for machine type @var{cpu_type}. Supported values for
+@var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
+@samp{c44}. The default is @samp{c40} to generate code for the
+TMS320C40.
+
+@item -mbig-memory
+@item -mbig
+@itemx -msmall-memory
+@itemx -msmall
+Generates code for the big or small memory model. The small memory
+model assumed that all data fits into one 64K word page. At run-time
+the data page (DP) register must be set to point to the 64K page
+containing the .bss and .data program sections. The big memory model is
+the default and requires reloading of the DP register for every direct
+memory access.
+
+@item -mbk
+@itemx -mno-bk
+Allow (disallow) allocation of general integer operands into the block
+count register BK.
+
+@item -mdb
+@itemx -mno-db
+Enable (disable) generation of code using decrement and branch,
+DBcond(D), instructions. This is enabled by default for the C4x. To be
+on the safe side, this is disabled for the C3x, since the maximum
+iteration count on the C3x is 2^23 + 1 (but who iterates loops more than
+2^23 times on the C3x?). Note that GCC will try to reverse a loop so
+that it can utilise the decrement and branch instruction, but will give
+up if there is more than one memory reference in the loop. Thus a loop
+where the loop counter is decremented can generate slightly more
+efficient code, in cases where the RPTB instruction cannot be utilised.
+
+@item -mdp-isr-reload
+@itemx -mparanoid
+Force the DP register to be saved on entry to an interrupt service
+routine (ISR), reloaded to point to the data section, and restored on
+exit from the ISR. This should not be required unless someone has
+violated the small memory model by modifying the DP register, say within
+an object library.
+
+@item -mmpyi
+@itemx -mno-mpyi
+For the C3x use the 24-bit MPYI instruction for integer multiplies
+instead of a library call to guarantee 32-bit results. Note that if one
+of the operands is a constant, then the multiplication will be performed
+using shifts and adds. If the -mmpyi option is not specified for the C3x,
+then squaring operations are performed inline instead of a library call.
+
+@item -mfast-fix
+@itemx -mno-fast-fix
+The C3x/C4x FIX instruction to convert a floating point value to an
+integer value chooses the nearest integer less than or equal to the
+floating point value rather than to the nearest integer. Thus if the
+floating point number is negative, the result will be incorrectly
+truncated an additional code is necessary to detect and correct this
+case. This option can be used to disable generation of the additional
+code required to correct the result.
+
+@item -mrptb
+@itemx -mno-rptb
+Enable (disable) generation of repeat block sequences using the RPTB
+instruction for zero overhead looping. The RPTB construct is only used
+for innermost loops that do not call functions or jump across the loop
+boundaries. There is no advantage having nested RPTB loops due to the
+overhead required to save and restore the RC, RS, and RE registers.
+This is enabled by default with -O2.
+
+@item -mrpts=@var{count}
+@itemx -mno-rpts
+Enable (disable) the use of the single instruction repeat instruction
+RPTS. If a repeat block contains a single instruction, and the loop
+count can be guaranteed to be less than the value @var{count}, GCC will
+emit a RPTS instruction instead of a RPTB. If no value is specified,
+then a RPTS will be emitted even if the loop count cannot be determined
+at compile time. Note that the repeated instruction following RPTS does
+not have to be reloaded from memory each iteration, thus freeing up the
+CPU buses for oeprands. However, since interrupts are blocked by this
+instruction, it is disabled by default.
+
+@item -mloop-unsigned
+@itemx -mno-loop-unsigned
+The maximum iteration count when using RPTS and RPTB (and DB on the C40)
+is 2^31 + 1 since these instructions test if the iteration count is
+negative to terminate the loop. If the iteration count is unsigned
+there is a possibility than the 2^31 + 1 maximum iteration count may be
+exceeded. This switch allows an unsigned iteration count.
+
+@item -mti
+Try to emit an assembler syntax that the TI assembler (asm30) is happy
+with. This also enforces compatibility with the API employed by the TI
+C3x C compiler. For example, long doubles are passed as structures
+rather than in floating point registers.
+
+@item -mregparm
+@itemx -mmemparm
+Generate code that uses registers (stack) for passing arguments to functions.
+By default, arguments are passed in registers where possible rather
+than by pushing arguments on to the stack.
+
+@item -mparallel-insns
+@itemx -mno-parallel-insns
+Allow the generation of parallel instructions. This is enabled by
+default with -O2.
+
+@item -mparallel-mpy
+@itemx -mno-parallel-mpy
+Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
+provided -mparallel-insns is also specified. These instructions have
+tight register constraints which can pessimize the code generation
+of large functions.
+
+@end table
+
@node V850 Options
@subsection V850 Options
@cindex V850 Options
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