/* Convert RTL to assembler code and output it, for GNU compiler.
- Copyright (C) 1987, 88, 89, 92-7, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
This file is part of GNU CC.
#else
#include <varargs.h>
#endif
-#include <stdio.h>
-#include <ctype.h>
-#if HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
+#include "system.h"
#include "tree.h"
#include "rtl.h"
#include "defaults.h"
#include "output.h"
#include "except.h"
+#include "toplev.h"
+#include "reload.h"
/* Get N_SLINE and N_SOL from stab.h if we can expect the file to exist. */
#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
-#if defined (USG) || defined (NO_STAB_H)
+#include "dbxout.h"
+#if defined (USG) || !defined (HAVE_STAB_H)
#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
#else
#include <stab.h> /* On BSD, use the system's stab.h. */
#include "xcoffout.h"
#endif
+#ifdef DWARF_DEBUGGING_INFO
+#include "dwarfout.h"
+#endif
+
+#if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO)
+#include "dwarf2out.h"
+#endif
+
+#ifdef SDB_DEBUGGING_INFO
+#include "sdbout.h"
+#endif
+
/* .stabd code for line number. */
#ifndef N_SLINE
#define N_SLINE 0x44
#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
#endif
+#ifndef JUMP_TABLES_IN_TEXT_SECTION
+#define JUMP_TABLES_IN_TEXT_SECTION 0
+#endif
+
/* Nonzero means this function is a leaf function, with no function calls.
This variable exists to be examined in FUNCTION_PROLOGUE
and FUNCTION_EPILOGUE. Always zero, unless set by some action. */
/* Number of instrumented arcs when profile_arc_flag is set. */
extern int count_instrumented_arcs;
+extern int length_unit_log; /* This is defined in insn-attrtab.c. */
+
/* Nonzero while outputting an `asm' with operands.
This means that inconsistencies are the user's fault, so don't abort.
The precise value is the insn being output, to pass to error_for_asm. */
static rtx this_is_asm_operands;
/* Number of operands of this insn, for an `asm' with operands. */
-static int insn_noperands;
+static unsigned int insn_noperands;
/* Compare optimization flag. */
/* Address of insn being processed. Used by `insn_current_length'. */
int insn_current_address;
+/* Address of insn being processed in previous iteration. */
+int insn_last_address;
+
+/* konwn invariant alignment of insn being processed. */
+int insn_current_align;
+
+/* After shorten_branches, for any insn, uid_align[INSN_UID (insn)]
+ gives the next following alignment insn that increases the known
+ alignment, or NULL_RTX if there is no such insn.
+ For any alignment obtained this way, we can again index uid_align with
+ its uid to obtain the next following align that in turn increases the
+ alignment, till we reach NULL_RTX; the sequence obtained this way
+ for each insn we'll call the alignment chain of this insn in the following
+ comments. */
+
+struct label_alignment {
+ short alignment;
+ short max_skip;
+};
+
+static rtx *uid_align;
+static int *uid_shuid;
+static struct label_alignment *label_align;
+
/* Indicate that branch shortening hasn't yet been done. */
void
init_insn_lengths ()
{
- insn_lengths = 0;
+ if (label_align)
+ {
+ free (label_align);
+ label_align = 0;
+ }
+ if (uid_shuid)
+ {
+ free (uid_shuid);
+ uid_shuid = 0;
+ }
+ if (insn_lengths)
+ {
+ free (insn_lengths);
+ insn_lengths = 0;
+ }
+ if (insn_addresses)
+ {
+ free (insn_addresses);
+ insn_addresses = 0;
+ }
+ if (uid_align)
+ {
+ free (uid_align);
+ uid_align = 0;
+ }
}
/* Obtain the current length of an insn. If branch shortening has been done,
body = PATTERN (insn);
if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
{
- /* This only takes room if jump tables go into the text section. */
-#if !defined(READONLY_DATA_SECTION) || defined(JUMP_TABLES_IN_TEXT_SECTION)
- length = (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
- * GET_MODE_SIZE (GET_MODE (body)));
-
- /* Be pessimistic and assume worst-case alignment. */
- length += (GET_MODE_SIZE (GET_MODE (body)) - 1);
-#else
- return 0;
-#endif
+ /* Alignment is machine-dependent and should be handled by
+ ADDR_VEC_ALIGN. */
}
else
length = insn_default_length (insn);
#endif /* not HAVE_ATTR_length */
}
\f
+/* Code to handle alignment inside shorten_branches. */
+
+/* Here is an explanation how the algorithm in align_fuzz can give
+ proper results:
+
+ Call a sequence of instructions beginning with alignment point X
+ and continuing until the next alignment point `block X'. When `X'
+ is used in an expression, it means the alignment value of the
+ alignment point.
+
+ Call the distance between the start of the first insn of block X, and
+ the end of the last insn of block X `IX', for the `inner size of X'.
+ This is clearly the sum of the instruction lengths.
+
+ Likewise with the next alignment-delimited block following X, which we
+ shall call block Y.
+
+ Call the distance between the start of the first insn of block X, and
+ the start of the first insn of block Y `OX', for the `outer size of X'.
+
+ The estimated padding is then OX - IX.
+
+ OX can be safely estimated as
+
+ if (X >= Y)
+ OX = round_up(IX, Y)
+ else
+ OX = round_up(IX, X) + Y - X
+
+ Clearly est(IX) >= real(IX), because that only depends on the
+ instruction lengths, and those being overestimated is a given.
+
+ Clearly round_up(foo, Z) >= round_up(bar, Z) if foo >= bar, so
+ we needn't worry about that when thinking about OX.
+
+ When X >= Y, the alignment provided by Y adds no uncertainty factor
+ for branch ranges starting before X, so we can just round what we have.
+ But when X < Y, we don't know anything about the, so to speak,
+ `middle bits', so we have to assume the worst when aligning up from an
+ address mod X to one mod Y, which is Y - X. */
+
+#ifndef LABEL_ALIGN
+#define LABEL_ALIGN(LABEL) 0
+#endif
+
+#ifndef LABEL_ALIGN_MAX_SKIP
+#define LABEL_ALIGN_MAX_SKIP 0
+#endif
+
+#ifndef LOOP_ALIGN
+#define LOOP_ALIGN(LABEL) 0
+#endif
+
+#ifndef LOOP_ALIGN_MAX_SKIP
+#define LOOP_ALIGN_MAX_SKIP 0
+#endif
+
+#ifndef LABEL_ALIGN_AFTER_BARRIER
+#define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0
+#endif
+
+#ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
+#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0
+#endif
+
+#ifndef ADDR_VEC_ALIGN
+int
+final_addr_vec_align (addr_vec)
+ rtx addr_vec;
+{
+ int align = exact_log2 (GET_MODE_SIZE (GET_MODE (PATTERN (addr_vec))));
+
+ if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT)
+ align = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
+ return align;
+
+}
+#define ADDR_VEC_ALIGN(ADDR_VEC) final_addr_vec_align (ADDR_VEC)
+#endif
+
+#ifndef INSN_LENGTH_ALIGNMENT
+#define INSN_LENGTH_ALIGNMENT(INSN) length_unit_log
+#endif
+
+#define INSN_SHUID(INSN) (uid_shuid[INSN_UID (INSN)])
+
+static int min_labelno, max_labelno;
+
+#define LABEL_TO_ALIGNMENT(LABEL) \
+ (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].alignment)
+
+#define LABEL_TO_MAX_SKIP(LABEL) \
+ (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].max_skip)
+
+/* For the benefit of port specific code do this also as a function. */
+int
+label_to_alignment (label)
+ rtx label;
+{
+ return LABEL_TO_ALIGNMENT (label);
+}
+
+#ifdef HAVE_ATTR_length
+/* The differences in addresses
+ between a branch and its target might grow or shrink depending on
+ the alignment the start insn of the range (the branch for a forward
+ branch or the label for a backward branch) starts out on; if these
+ differences are used naively, they can even oscillate infinitely.
+ We therefore want to compute a 'worst case' address difference that
+ is independent of the alignment the start insn of the range end
+ up on, and that is at least as large as the actual difference.
+ The function align_fuzz calculates the amount we have to add to the
+ naively computed difference, by traversing the part of the alignment
+ chain of the start insn of the range that is in front of the end insn
+ of the range, and considering for each alignment the maximum amount
+ that it might contribute to a size increase.
+
+ For casesi tables, we also want to know worst case minimum amounts of
+ address difference, in case a machine description wants to introduce
+ some common offset that is added to all offsets in a table.
+ For this purpose, align_fuzz with a growth argument of 0 comuptes the
+ appropriate adjustment. */
+
+
+/* Compute the maximum delta by which the difference of the addresses of
+ START and END might grow / shrink due to a different address for start
+ which changes the size of alignment insns between START and END.
+ KNOWN_ALIGN_LOG is the alignment known for START.
+ GROWTH should be ~0 if the objective is to compute potential code size
+ increase, and 0 if the objective is to compute potential shrink.
+ The return value is undefined for any other value of GROWTH. */
+int
+align_fuzz (start, end, known_align_log, growth)
+ rtx start, end;
+ int known_align_log;
+ unsigned growth;
+{
+ int uid = INSN_UID (start);
+ rtx align_label;
+ int known_align = 1 << known_align_log;
+ int end_shuid = INSN_SHUID (end);
+ int fuzz = 0;
+
+ for (align_label = uid_align[uid]; align_label; align_label = uid_align[uid])
+ {
+ int align_addr, new_align;
+
+ uid = INSN_UID (align_label);
+ align_addr = insn_addresses[uid] - insn_lengths[uid];
+ if (uid_shuid[uid] > end_shuid)
+ break;
+ known_align_log = LABEL_TO_ALIGNMENT (align_label);
+ new_align = 1 << known_align_log;
+ if (new_align < known_align)
+ continue;
+ fuzz += (-align_addr ^ growth) & (new_align - known_align);
+ known_align = new_align;
+ }
+ return fuzz;
+}
+
+/* Compute a worst-case reference address of a branch so that it
+ can be safely used in the presence of aligned labels. Since the
+ size of the branch itself is unknown, the size of the branch is
+ not included in the range. I.e. for a forward branch, the reference
+ address is the end address of the branch as known from the previous
+ branch shortening pass, minus a value to account for possible size
+ increase due to alignment. For a backward branch, it is the start
+ address of the branch as known from the current pass, plus a value
+ to account for possible size increase due to alignment.
+ NB.: Therefore, the maximum offset allowed for backward branches needs
+ to exclude the branch size. */
+int
+insn_current_reference_address (branch)
+ rtx branch;
+{
+ rtx dest;
+ rtx seq = NEXT_INSN (PREV_INSN (branch));
+ int seq_uid = INSN_UID (seq);
+ if (GET_CODE (branch) != JUMP_INSN)
+ /* This can happen for example on the PA; the objective is to know the
+ offset to address something in front of the start of the function.
+ Thus, we can treat it like a backward branch.
+ We assume here that FUNCTION_BOUNDARY / BITS_PER_UNIT is larger than
+ any alignment we'd encounter, so we skip the call to align_fuzz. */
+ return insn_current_address;
+ dest = JUMP_LABEL (branch);
+ /* BRANCH has no proper alignment chain set, so use SEQ. */
+ if (INSN_SHUID (branch) < INSN_SHUID (dest))
+ {
+ /* Forward branch. */
+ return (insn_last_address + insn_lengths[seq_uid]
+ - align_fuzz (seq, dest, length_unit_log, ~0));
+ }
+ else
+ {
+ /* Backward branch. */
+ return (insn_current_address
+ + align_fuzz (dest, seq, length_unit_log, ~0));
+ }
+}
+#endif /* HAVE_ATTR_length */
+\f
/* Make a pass over all insns and compute their actual lengths by shortening
any branches of variable length if possible. */
#define FIRST_INSN_ADDRESS 0
#endif
+/* shorten_branches might be called multiple times: for example, the SH
+ port splits out-of-range conditional branches in MACHINE_DEPENDENT_REORG.
+ In order to do this, it needs proper length information, which it obtains
+ by calling shorten_branches. This cannot be collapsed with
+ shorten_branches itself into a single pass unless we also want to intergate
+ reorg.c, since the branch splitting exposes new instructions with delay
+ slots. */
+
void
shorten_branches (first)
rtx first;
{
-#ifdef HAVE_ATTR_length
rtx insn;
+ int max_uid;
+ int i;
+ int max_log;
+ int max_skip;
+#ifdef HAVE_ATTR_length
+#define MAX_CODE_ALIGN 16
+ rtx seq;
int something_changed = 1;
- int max_uid = 0;
char *varying_length;
rtx body;
int uid;
+ rtx align_tab[MAX_CODE_ALIGN];
/* In order to make sure that all instructions have valid length info,
we must split them before we compute the address/length info. */
for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
- insn = try_split (PATTERN (insn), insn, 1);
+ {
+ rtx old = insn;
+ insn = try_split (PATTERN (old), old, 1);
+ /* When not optimizing, the old insn will be still left around
+ with only the 'deleted' bit set. Transform it into a note
+ to avoid confusion of subsequent processing. */
+ if (INSN_DELETED_P (old))
+ {
+ PUT_CODE (old , NOTE);
+ NOTE_LINE_NUMBER (old) = NOTE_INSN_DELETED;
+ NOTE_SOURCE_FILE (old) = 0;
+ }
+ }
+#endif
- /* Compute maximum UID and allocate arrays. */
- for (insn = first; insn; insn = NEXT_INSN (insn))
- if (INSN_UID (insn) > max_uid)
- max_uid = INSN_UID (insn);
+ /* We must do some computations even when not actually shortening, in
+ order to get the alignment information for the labels. */
+
+ init_insn_lengths ();
+
+ /* Compute maximum UID and allocate label_align / uid_shuid. */
+ max_uid = get_max_uid ();
+
+ max_labelno = max_label_num ();
+ min_labelno = get_first_label_num ();
+ label_align = (struct label_alignment *) xmalloc (
+ (max_labelno - min_labelno + 1) * sizeof (struct label_alignment));
+ bzero (label_align,
+ (max_labelno - min_labelno + 1) * sizeof (struct label_alignment));
+
+ uid_shuid = (int *) xmalloc (max_uid * sizeof *uid_shuid);
+
+ /* Initialize label_align and set up uid_shuid to be strictly
+ monotonically rising with insn order. */
+ /* We use max_log here to keep track of the maximum alignment we want to
+ impose on the next CODE_LABEL (or the current one if we are processing
+ the CODE_LABEL itself). */
+
+ max_log = 0;
+ max_skip = 0;
+
+ for (insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn))
+ {
+ int log;
+
+ INSN_SHUID (insn) = i++;
+ if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+ {
+ /* reorg might make the first insn of a loop being run once only,
+ and delete the label in front of it. Then we want to apply
+ the loop alignment to the new label created by reorg, which
+ is separated by the former loop start insn from the
+ NOTE_INSN_LOOP_BEG. */
+ }
+ else if (GET_CODE (insn) == CODE_LABEL)
+ {
+ rtx next;
+
+ log = LABEL_ALIGN (insn);
+ if (max_log < log)
+ {
+ max_log = log;
+ max_skip = LABEL_ALIGN_MAX_SKIP;
+ }
+ next = NEXT_INSN (insn);
+ /* ADDR_VECs only take room if read-only data goes into the text
+ section. */
+ if (JUMP_TABLES_IN_TEXT_SECTION
+#if !defined(READONLY_DATA_SECTION)
+ || 1
+#endif
+ )
+ if (next && GET_CODE (next) == JUMP_INSN)
+ {
+ rtx nextbody = PATTERN (next);
+ if (GET_CODE (nextbody) == ADDR_VEC
+ || GET_CODE (nextbody) == ADDR_DIFF_VEC)
+ {
+ log = ADDR_VEC_ALIGN (next);
+ if (max_log < log)
+ {
+ max_log = log;
+ max_skip = LABEL_ALIGN_MAX_SKIP;
+ }
+ }
+ }
+ LABEL_TO_ALIGNMENT (insn) = max_log;
+ LABEL_TO_MAX_SKIP (insn) = max_skip;
+ max_log = 0;
+ max_skip = 0;
+ }
+ else if (GET_CODE (insn) == BARRIER)
+ {
+ rtx label;
+
+ for (label = insn; label && GET_RTX_CLASS (GET_CODE (label)) != 'i';
+ label = NEXT_INSN (label))
+ if (GET_CODE (label) == CODE_LABEL)
+ {
+ log = LABEL_ALIGN_AFTER_BARRIER (insn);
+ if (max_log < log)
+ {
+ max_log = log;
+ max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP;
+ }
+ break;
+ }
+ }
+ /* Again, we allow NOTE_INSN_LOOP_BEG - INSN - CODE_LABEL
+ sequences in order to handle reorg output efficiently. */
+ else if (GET_CODE (insn) == NOTE
+ && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
+ {
+ rtx label;
+
+ for (label = insn; label; label = NEXT_INSN (label))
+ if (GET_CODE (label) == CODE_LABEL)
+ {
+ log = LOOP_ALIGN (insn);
+ if (max_log < log)
+ {
+ max_log = log;
+ max_skip = LOOP_ALIGN_MAX_SKIP;
+ }
+ break;
+ }
+ }
+ else
+ continue;
+ }
+#ifdef HAVE_ATTR_length
+
+ /* Allocate the rest of the arrays. */
+ insn_lengths = (short *) xmalloc (max_uid * sizeof (short));
+ insn_addresses = (int *) xmalloc (max_uid * sizeof (int));
+ /* Syntax errors can lead to labels being outside of the main insn stream.
+ Initialize insn_addresses, so that we get reproducible results. */
+ bzero ((char *)insn_addresses, max_uid * sizeof *insn_addresses);
+ uid_align = (rtx *) xmalloc (max_uid * sizeof *uid_align);
+
+ varying_length = (char *) xmalloc (max_uid * sizeof (char));
+
+ bzero (varying_length, max_uid);
+
+ /* Initialize uid_align. We scan instructions
+ from end to start, and keep in align_tab[n] the last seen insn
+ that does an alignment of at least n+1, i.e. the successor
+ in the alignment chain for an insn that does / has a known
+ alignment of n. */
+
+ bzero ((char *) uid_align, max_uid * sizeof *uid_align);
+
+ for (i = MAX_CODE_ALIGN; --i >= 0; )
+ align_tab[i] = NULL_RTX;
+ seq = get_last_insn ();
+ for (; seq; seq = PREV_INSN (seq))
+ {
+ int uid = INSN_UID (seq);
+ int log;
+ log = (GET_CODE (seq) == CODE_LABEL ? LABEL_TO_ALIGNMENT (seq) : 0);
+ uid_align[uid] = align_tab[0];
+ if (log)
+ {
+ /* Found an alignment label. */
+ uid_align[uid] = align_tab[log];
+ for (i = log - 1; i >= 0; i--)
+ align_tab[i] = seq;
+ }
+ }
+#ifdef CASE_VECTOR_SHORTEN_MODE
+ if (optimize)
+ {
+ /* Look for ADDR_DIFF_VECs, and initialize their minimum and maximum
+ label fields. */
+
+ int min_shuid = INSN_SHUID (get_insns ()) - 1;
+ int max_shuid = INSN_SHUID (get_last_insn ()) + 1;
+ int rel;
+
+ for (insn = first; insn != 0; insn = NEXT_INSN (insn))
+ {
+ rtx min_lab = NULL_RTX, max_lab = NULL_RTX, pat;
+ int len, i, min, max, insn_shuid;
+ int min_align;
+ addr_diff_vec_flags flags;
+
+ if (GET_CODE (insn) != JUMP_INSN
+ || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
+ continue;
+ pat = PATTERN (insn);
+ len = XVECLEN (pat, 1);
+ if (len <= 0)
+ abort ();
+ min_align = MAX_CODE_ALIGN;
+ for (min = max_shuid, max = min_shuid, i = len - 1; i >= 0; i--)
+ {
+ rtx lab = XEXP (XVECEXP (pat, 1, i), 0);
+ int shuid = INSN_SHUID (lab);
+ if (shuid < min)
+ {
+ min = shuid;
+ min_lab = lab;
+ }
+ if (shuid > max)
+ {
+ max = shuid;
+ max_lab = lab;
+ }
+ if (min_align > LABEL_TO_ALIGNMENT (lab))
+ min_align = LABEL_TO_ALIGNMENT (lab);
+ }
+ XEXP (pat, 2) = gen_rtx_LABEL_REF (VOIDmode, min_lab);
+ XEXP (pat, 3) = gen_rtx_LABEL_REF (VOIDmode, max_lab);
+ insn_shuid = INSN_SHUID (insn);
+ rel = INSN_SHUID (XEXP (XEXP (pat, 0), 0));
+ flags.min_align = min_align;
+ flags.base_after_vec = rel > insn_shuid;
+ flags.min_after_vec = min > insn_shuid;
+ flags.max_after_vec = max > insn_shuid;
+ flags.min_after_base = min > rel;
+ flags.max_after_base = max > rel;
+ ADDR_DIFF_VEC_FLAGS (pat) = flags;
+ }
+ }
+#endif /* CASE_VECTOR_SHORTEN_MODE */
- max_uid++;
- insn_lengths = (short *) oballoc (max_uid * sizeof (short));
- insn_addresses = (int *) oballoc (max_uid * sizeof (int));
- varying_length = (char *) oballoc (max_uid * sizeof (char));
/* Compute initial lengths, addresses, and varying flags for each insn. */
for (insn_current_address = FIRST_INSN_ADDRESS, insn = first;
insn_current_address += insn_lengths[uid], insn = NEXT_INSN (insn))
{
uid = INSN_UID (insn);
- insn_addresses[uid] = insn_current_address;
+
insn_lengths[uid] = 0;
- varying_length[uid] = 0;
+
+ if (GET_CODE (insn) == CODE_LABEL)
+ {
+ int log = LABEL_TO_ALIGNMENT (insn);
+ if (log)
+ {
+ int align = 1 << log;
+ int new_address = (insn_current_address + align - 1) & -align;
+ insn_lengths[uid] = new_address - insn_current_address;
+ insn_current_address = new_address;
+ }
+ }
+
+ insn_addresses[uid] = insn_current_address;
if (GET_CODE (insn) == NOTE || GET_CODE (insn) == BARRIER
|| GET_CODE (insn) == CODE_LABEL)
{
/* This only takes room if read-only data goes into the text
section. */
-#if !defined(READONLY_DATA_SECTION) || defined(JUMP_TABLES_IN_TEXT_SECTION)
- int unitsize = GET_MODE_SIZE (GET_MODE (body));
-
- insn_lengths[uid] = (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
- * GET_MODE_SIZE (GET_MODE (body)));
-
- /* We don't know what address the ADDR_VEC/ADDR_DIFF_VEC will end
- up at after branch shortening. As a result, it is impossible
- to determine how much padding we need at this point. Therefore,
- assume worst possible alignment. */
- insn_lengths[uid] += unitsize - 1;
-
-#else
- ;
-#endif
+ if (JUMP_TABLES_IN_TEXT_SECTION
+#if !defined(READONLY_DATA_SECTION)
+ || 1
+#endif
+ )
+ insn_lengths[uid] = (XVECLEN (body,
+ GET_CODE (body) == ADDR_DIFF_VEC)
+ * GET_MODE_SIZE (GET_MODE (body)));
+ /* Alignment is handled by ADDR_VEC_ALIGN. */
}
else if (asm_noperands (body) >= 0)
insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn);
while (something_changed)
{
something_changed = 0;
+ insn_current_align = MAX_CODE_ALIGN - 1;
for (insn_current_address = FIRST_INSN_ADDRESS, insn = first;
insn != 0;
insn = NEXT_INSN (insn))
{
int new_length;
-#ifdef SHORTEN_WITH_ADJUST_INSN_LENGTH
#ifdef ADJUST_INSN_LENGTH
int tmp_length;
#endif
-#endif
+ int length_align;
uid = INSN_UID (insn);
+
+ if (GET_CODE (insn) == CODE_LABEL)
+ {
+ int log = LABEL_TO_ALIGNMENT (insn);
+ if (log > insn_current_align)
+ {
+ int align = 1 << log;
+ int new_address= (insn_current_address + align - 1) & -align;
+ insn_lengths[uid] = new_address - insn_current_address;
+ insn_current_align = log;
+ insn_current_address = new_address;
+ }
+ else
+ insn_lengths[uid] = 0;
+ insn_addresses[uid] = insn_current_address;
+ continue;
+ }
+
+ length_align = INSN_LENGTH_ALIGNMENT (insn);
+ if (length_align < insn_current_align)
+ insn_current_align = length_align;
+
+ insn_last_address = insn_addresses[uid];
insn_addresses[uid] = insn_current_address;
- if (! varying_length[uid])
+
+#ifdef CASE_VECTOR_SHORTEN_MODE
+ if (optimize && GET_CODE (insn) == JUMP_INSN
+ && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
+ {
+ rtx body = PATTERN (insn);
+ int old_length = insn_lengths[uid];
+ rtx rel_lab = XEXP (XEXP (body, 0), 0);
+ rtx min_lab = XEXP (XEXP (body, 2), 0);
+ rtx max_lab = XEXP (XEXP (body, 3), 0);
+ addr_diff_vec_flags flags = ADDR_DIFF_VEC_FLAGS (body);
+ int rel_addr = insn_addresses[INSN_UID (rel_lab)];
+ int min_addr = insn_addresses[INSN_UID (min_lab)];
+ int max_addr = insn_addresses[INSN_UID (max_lab)];
+ rtx prev;
+ int rel_align = 0;
+
+ /* Try to find a known alignment for rel_lab. */
+ for (prev = rel_lab;
+ prev
+ && ! insn_lengths[INSN_UID (prev)]
+ && ! (varying_length[INSN_UID (prev)] & 1);
+ prev = PREV_INSN (prev))
+ if (varying_length[INSN_UID (prev)] & 2)
+ {
+ rel_align = LABEL_TO_ALIGNMENT (prev);
+ break;
+ }
+
+ /* See the comment on addr_diff_vec_flags in rtl.h for the
+ meaning of the flags values. base: REL_LAB vec: INSN */
+ /* Anything after INSN has still addresses from the last
+ pass; adjust these so that they reflect our current
+ estimate for this pass. */
+ if (flags.base_after_vec)
+ rel_addr += insn_current_address - insn_last_address;
+ if (flags.min_after_vec)
+ min_addr += insn_current_address - insn_last_address;
+ if (flags.max_after_vec)
+ max_addr += insn_current_address - insn_last_address;
+ /* We want to know the worst case, i.e. lowest possible value
+ for the offset of MIN_LAB. If MIN_LAB is after REL_LAB,
+ its offset is positive, and we have to be wary of code shrink;
+ otherwise, it is negative, and we have to be vary of code
+ size increase. */
+ if (flags.min_after_base)
+ {
+ /* If INSN is between REL_LAB and MIN_LAB, the size
+ changes we are about to make can change the alignment
+ within the observed offset, therefore we have to break
+ it up into two parts that are independent. */
+ if (! flags.base_after_vec && flags.min_after_vec)
+ {
+ min_addr -= align_fuzz (rel_lab, insn, rel_align, 0);
+ min_addr -= align_fuzz (insn, min_lab, 0, 0);
+ }
+ else
+ min_addr -= align_fuzz (rel_lab, min_lab, rel_align, 0);
+ }
+ else
+ {
+ if (flags.base_after_vec && ! flags.min_after_vec)
+ {
+ min_addr -= align_fuzz (min_lab, insn, 0, ~0);
+ min_addr -= align_fuzz (insn, rel_lab, 0, ~0);
+ }
+ else
+ min_addr -= align_fuzz (min_lab, rel_lab, 0, ~0);
+ }
+ /* Likewise, determine the highest lowest possible value
+ for the offset of MAX_LAB. */
+ if (flags.max_after_base)
+ {
+ if (! flags.base_after_vec && flags.max_after_vec)
+ {
+ max_addr += align_fuzz (rel_lab, insn, rel_align, ~0);
+ max_addr += align_fuzz (insn, max_lab, 0, ~0);
+ }
+ else
+ max_addr += align_fuzz (rel_lab, max_lab, rel_align, ~0);
+ }
+ else
+ {
+ if (flags.base_after_vec && ! flags.max_after_vec)
+ {
+ max_addr += align_fuzz (max_lab, insn, 0, 0);
+ max_addr += align_fuzz (insn, rel_lab, 0, 0);
+ }
+ else
+ max_addr += align_fuzz (max_lab, rel_lab, 0, 0);
+ }
+ PUT_MODE (body, CASE_VECTOR_SHORTEN_MODE (min_addr - rel_addr,
+ max_addr - rel_addr,
+ body));
+ if (JUMP_TABLES_IN_TEXT_SECTION
+#if !defined(READONLY_DATA_SECTION)
+ || 1
+#endif
+ )
+ {
+ insn_lengths[uid]
+ = (XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)));
+ insn_current_address += insn_lengths[uid];
+ if (insn_lengths[uid] != old_length)
+ something_changed = 1;
+ }
+
+ continue;
+ }
+#endif /* CASE_VECTOR_SHORTEN_MODE */
+
+ if (! (varying_length[uid]))
{
insn_current_address += insn_lengths[uid];
continue;
insn_current_address += new_length;
}
-#ifdef SHORTEN_WITH_ADJUST_INSN_LENGTH
#ifdef ADJUST_INSN_LENGTH
/* If needed, do any adjustment. */
tmp_length = new_length;
ADJUST_INSN_LENGTH (insn, new_length);
insn_current_address += (new_length - tmp_length);
#endif
-#endif
if (new_length != insn_lengths[uid])
{
if (!optimize)
break;
}
+
+ free (varying_length);
+
#endif /* HAVE_ATTR_length */
}
{
register rtx insn;
int max_line = 0;
+ int max_uid = 0;
last_ignored_compare = 0;
new_block = 1;
bzero (line_note_exists, max_line + 1);
for (insn = first; insn; insn = NEXT_INSN (insn))
- if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
- line_note_exists[NOTE_LINE_NUMBER (insn)] = 1;
+ {
+ if (INSN_UID (insn) > max_uid) /* find largest UID */
+ max_uid = INSN_UID (insn);
+ if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
+ line_note_exists[NOTE_LINE_NUMBER (insn)] = 1;
+ }
+
+ /* Initialize insn_eh_region table if eh is being used. */
+
+ init_insn_eh_region (first, max_uid);
init_recog ();
if the last insn was a conditional branch. */
if (profile_block_flag && new_block)
add_bb (file);
+
+ free_insn_eh_region ();
}
\f
/* The final scan for one insn, INSN.
/* Align the beginning of a loop, for higher speed
on certain machines. */
- if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG && optimize > 0)
- {
-#ifdef ASM_OUTPUT_LOOP_ALIGN
- rtx next = next_nonnote_insn (insn);
- if (next && GET_CODE (next) == CODE_LABEL)
- {
- ASM_OUTPUT_LOOP_ALIGN (asm_out_file);
- }
-#endif
- break;
- }
+ if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
+ break; /* This used to depend on optimize, but that was bogus. */
if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
break;
&& ! exceptions_via_longjmp)
{
ASM_OUTPUT_INTERNAL_LABEL (file, "LEHB", NOTE_BLOCK_NUMBER (insn));
- add_eh_table_entry (NOTE_BLOCK_NUMBER (insn));
+ if (! flag_new_exceptions)
+ add_eh_table_entry (NOTE_BLOCK_NUMBER (insn));
#ifdef ASM_OUTPUT_EH_REGION_BEG
ASM_OUTPUT_EH_REGION_BEG (file, NOTE_BLOCK_NUMBER (insn));
#endif
&& ! exceptions_via_longjmp)
{
ASM_OUTPUT_INTERNAL_LABEL (file, "LEHE", NOTE_BLOCK_NUMBER (insn));
+ if (flag_new_exceptions)
+ add_eh_table_entry (NOTE_BLOCK_NUMBER (insn));
#ifdef ASM_OUTPUT_EH_REGION_END
ASM_OUTPUT_EH_REGION_END (file, NOTE_BLOCK_NUMBER (insn));
#endif
break;
case BARRIER:
-#ifdef ASM_OUTPUT_ALIGN_CODE
- /* Don't litter the assembler output with needless alignments. A
- BARRIER will be placed at the end of every function if HAVE_epilogue
- is true. */
- if (NEXT_INSN (insn))
- ASM_OUTPUT_ALIGN_CODE (file);
-#endif
#if defined (DWARF2_UNWIND_INFO) && !defined (ACCUMULATE_OUTGOING_ARGS)
/* If we push arguments, we need to check all insns for stack
adjustments. */
break;
case CODE_LABEL:
+ /* The target port might emit labels in the output function for
+ some insn, e.g. sh.c output_branchy_insn. */
+ if (CODE_LABEL_NUMBER (insn) <= max_labelno)
+ {
+ int align = LABEL_TO_ALIGNMENT (insn);
+#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
+ int max_skip = LABEL_TO_MAX_SKIP (insn);
+#endif
+
+ if (align && NEXT_INSN (insn))
+#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
+ ASM_OUTPUT_MAX_SKIP_ALIGN (file, align, max_skip);
+#else
+ ASM_OUTPUT_ALIGN (file, align);
+#endif
+ }
CC_STATUS_INIT;
if (prescan > 0)
break;
if (GET_CODE (nextbody) == ADDR_VEC
|| GET_CODE (nextbody) == ADDR_DIFF_VEC)
{
-#ifndef JUMP_TABLES_IN_TEXT_SECTION
- readonly_data_section ();
+ if (! JUMP_TABLES_IN_TEXT_SECTION)
+ {
+ readonly_data_section ();
#ifdef READONLY_DATA_SECTION
- ASM_OUTPUT_ALIGN (file,
- exact_log2 (BIGGEST_ALIGNMENT
- / BITS_PER_UNIT));
+ ASM_OUTPUT_ALIGN (file,
+ exact_log2 (BIGGEST_ALIGNMENT
+ / BITS_PER_UNIT));
#endif /* READONLY_DATA_SECTION */
-#else /* JUMP_TABLES_IN_TEXT_SECTION */
- function_section (current_function_decl);
-#endif /* JUMP_TABLES_IN_TEXT_SECTION */
+ }
+ else
+ function_section (current_function_decl);
+
#ifdef ASM_OUTPUT_CASE_LABEL
ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn),
NEXT_INSN (insn));
#ifdef ASM_OUTPUT_ADDR_DIFF_ELT
ASM_OUTPUT_ADDR_DIFF_ELT
(file,
+ body,
CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0)));
#else
/* Detect `asm' construct with operands. */
if (asm_noperands (body) >= 0)
{
- int noperands = asm_noperands (body);
+ unsigned int noperands = asm_noperands (body);
rtx *ops = (rtx *) alloca (noperands * sizeof (rtx));
char *string;
/* If we didn't split the insn, go away. */
if (new == insn && PATTERN (new) == body)
- abort ();
+ fatal_insn ("Could not split insn", insn);
#ifdef HAVE_ATTR_length
/* This instruction should have been split in shorten_branches,
register rtx x;
{
register rtx y = SUBREG_REG (x);
+
if (GET_CODE (y) == SUBREG)
y = alter_subreg (y);
+ /* If reload is operating, we may be replacing inside this SUBREG.
+ Check for that and make a new one if so. */
+ if (reload_in_progress && find_replacement (&SUBREG_REG (x)) != 0)
+ x = copy_rtx (x);
+
if (GET_CODE (y) == REG)
{
- /* If the containing reg really gets a hard reg, so do we. */
+ /* If the word size is larger than the size of this register,
+ adjust the register number to compensate. */
+ /* ??? Note that this just catches stragglers created by/for
+ integrate. It would be better if we either caught these
+ earlier, or kept _all_ subregs until now and eliminate
+ gen_lowpart and friends. */
+
PUT_CODE (x, REG);
+#ifdef ALTER_HARD_SUBREG
+ REGNO (x) = ALTER_HARD_SUBREG(GET_MODE (x), SUBREG_WORD (x),
+ GET_MODE (y), REGNO (y));
+#else
REGNO (x) = REGNO (y) + SUBREG_WORD (x);
+#endif
}
else if (GET_CODE (y) == MEM)
{
if (this_is_asm_operands)
error_for_asm (this_is_asm_operands, "invalid `asm': %s", str);
else
- abort ();
+ fatal ("Internal compiler error, output_operand_lossage `%s'", str);
}
\f
/* Output of assembler code from a template, and its subroutines. */
if (! (*p >= '0' && *p <= '9'))
output_operand_lossage ("operand number missing after %-letter");
- else if (this_is_asm_operands && c >= (unsigned) insn_noperands)
+ else if (this_is_asm_operands && (c < 0 || (unsigned int) c >= insn_noperands))
output_operand_lossage ("operand number out of range");
else if (letter == 'l')
output_asm_label (operands[c]);
else if (*p >= '0' && *p <= '9')
{
c = atoi (p);
- if (this_is_asm_operands && c >= (unsigned) insn_noperands)
+ if (this_is_asm_operands && (c < 0 || (unsigned int) c >= insn_noperands))
output_operand_lossage ("operand number out of range");
else
output_operand (operands[c], 0);
if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
{
/* In this case the CONST_INT holds both target words.
- Extract the bits from it into two word-sized pieces. */
+ Extract the bits from it into two word-sized pieces.
+ Sign extend each half to HOST_WIDE_INT. */
rtx low, high;
- HOST_WIDE_INT word_mask;
- /* Avoid warnings for shift count >= BITS_PER_WORD. */
- int shift_count = BITS_PER_WORD - 1;
-
- word_mask = (HOST_WIDE_INT) 1 << shift_count;
- word_mask |= word_mask - 1;
- low = GEN_INT (INTVAL (value) & word_mask);
- high = GEN_INT ((INTVAL (value) >> (shift_count + 1)) & word_mask);
+ /* On machines where HOST_BITS_PER_WIDE_INT == BITS_PER_WORD
+ the shift below will cause a compiler warning, even though
+ this code won't be executed. So put the shift amounts in
+ variables to avoid the warning. */
+ int rshift = HOST_BITS_PER_WIDE_INT - BITS_PER_WORD;
+ int lshift = HOST_BITS_PER_WIDE_INT - 2 * BITS_PER_WORD;
+
+ low = GEN_INT ((INTVAL (value) << rshift) >> rshift);
+ high = GEN_INT ((INTVAL (value) << lshift) >> rshift);
if (WORDS_BIG_ENDIAN)
{
*first = high;
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- {
- if ((regs_ever_live[i] || global_regs[i])
- && ! permitted_reg_in_leaf_functions[i])
- return 0;
- }
+ if ((regs_ever_live[i] || global_regs[i])
+ && ! permitted_reg_in_leaf_functions[i])
+ return 0;
+
+ if (current_function_uses_pic_offset_table
+ && pic_offset_table_rtx != 0
+ && GET_CODE (pic_offset_table_rtx) == REG
+ && ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)])
+ return 0;
+
return 1;
}
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