/* Convert RTL to assembler code and output it, for GNU compiler.
- Copyright (C) 1987, 88, 89, 92-7, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
This file is part of GNU CC.
FUNCTION_EPILOGUE. Those instructions never exist as rtl. */
#include "config.h"
-#ifdef __STDC__
-#include <stdarg.h>
-#else
-#include <varargs.h>
-#endif
-#include <stdio.h>
-#include <ctype.h>
-#if HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
+#include "system.h"
#include "tree.h"
#include "rtl.h"
#include "defaults.h"
#include "output.h"
#include "except.h"
+#include "toplev.h"
+#include "reload.h"
/* Get N_SLINE and N_SOL from stab.h if we can expect the file to exist. */
#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
-#if defined (USG) || defined (NO_STAB_H)
+#include "dbxout.h"
+#if defined (USG) || !defined (HAVE_STAB_H)
#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
#else
-#include <stab.h> /* On BSD, use the system's stab.h. */
-#endif /* not USG */
+#include <stab.h>
+#endif
+
#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
#ifdef XCOFF_DEBUGGING_INFO
#include "xcoffout.h"
#endif
+#ifdef DWARF_DEBUGGING_INFO
+#include "dwarfout.h"
+#endif
+
+#if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO)
+#include "dwarf2out.h"
+#endif
+
+#ifdef SDB_DEBUGGING_INFO
+#include "sdbout.h"
+#endif
+
/* .stabd code for line number. */
#ifndef N_SLINE
#define N_SLINE 0x44
#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
#endif
+#ifndef JUMP_TABLES_IN_TEXT_SECTION
+#define JUMP_TABLES_IN_TEXT_SECTION 0
+#endif
+
/* Nonzero means this function is a leaf function, with no function calls.
This variable exists to be examined in FUNCTION_PROLOGUE
and FUNCTION_EPILOGUE. Always zero, unless set by some action. */
static rtx this_is_asm_operands;
/* Number of operands of this insn, for an `asm' with operands. */
-static int insn_noperands;
+static unsigned int insn_noperands;
/* Compare optimization flag. */
/* konwn invariant alignment of insn being processed. */
int insn_current_align;
+/* After shorten_branches, for any insn, uid_align[INSN_UID (insn)]
+ gives the next following alignment insn that increases the known
+ alignment, or NULL_RTX if there is no such insn.
+ For any alignment obtained this way, we can again index uid_align with
+ its uid to obtain the next following align that in turn increases the
+ alignment, till we reach NULL_RTX; the sequence obtained this way
+ for each insn we'll call the alignment chain of this insn in the following
+ comments. */
+
+struct label_alignment {
+ short alignment;
+ short max_skip;
+};
+
+static rtx *uid_align;
+static int *uid_shuid;
+static struct label_alignment *label_align;
+
/* Indicate that branch shortening hasn't yet been done. */
void
init_insn_lengths ()
{
- insn_lengths = 0;
+ if (label_align)
+ {
+ free (label_align);
+ label_align = 0;
+ }
+ if (uid_shuid)
+ {
+ free (uid_shuid);
+ uid_shuid = 0;
+ }
+ if (insn_lengths)
+ {
+ free (insn_lengths);
+ insn_lengths = 0;
+ }
+ if (insn_addresses)
+ {
+ free (insn_addresses);
+ insn_addresses = 0;
+ }
+ if (uid_align)
+ {
+ free (uid_align);
+ uid_align = 0;
+ }
}
/* Obtain the current length of an insn. If branch shortening has been done,
#define LABEL_ALIGN(LABEL) 0
#endif
+#ifndef LABEL_ALIGN_MAX_SKIP
+#define LABEL_ALIGN_MAX_SKIP 0
+#endif
+
#ifndef LOOP_ALIGN
#define LOOP_ALIGN(LABEL) 0
#endif
+#ifndef LOOP_ALIGN_MAX_SKIP
+#define LOOP_ALIGN_MAX_SKIP 0
+#endif
+
#ifndef LABEL_ALIGN_AFTER_BARRIER
#define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0
#endif
+#ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
+#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0
+#endif
+
#ifndef ADDR_VEC_ALIGN
int
final_addr_vec_align (addr_vec)
#define INSN_LENGTH_ALIGNMENT(INSN) length_unit_log
#endif
-/* For any insn, uid_align[INSN_UID (insn)] gives the next following
- alignment insn that increases the known alignment, or NULL_RTX if
- there is no such insn.
- For any alignment obtained this way, we can again index uid_align with
- its uid to obtain the next following align that in turn increases the
- alignment, till we reach NULL_RTX; the sequence obtained this way
- for each insn we'll call the alignment chain of this insn in the following
- comments. */
-
-rtx *uid_align;
-int *uid_shuid;
-short *label_align; /* sh.c needs this to calculate constant tables. */
-
#define INSN_SHUID(INSN) (uid_shuid[INSN_UID (INSN)])
-static int min_labelno;
+static int min_labelno, max_labelno;
#define LABEL_TO_ALIGNMENT(LABEL) \
- (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno])
+ (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].alignment)
+
+#define LABEL_TO_MAX_SKIP(LABEL) \
+ (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].max_skip)
/* For the benefit of port specific code do this also as a function. */
int
GROWTH should be ~0 if the objective is to compute potential code size
increase, and 0 if the objective is to compute potential shrink.
The return value is undefined for any other value of GROWTH. */
-int align_fuzz (start, end, known_align_log, growth)
+int
+align_fuzz (start, end, known_align_log, growth)
rtx start, end;
int known_align_log;
unsigned growth;
any alignment we'd encounter, so we skip the call to align_fuzz. */
return insn_current_address;
dest = JUMP_LABEL (branch);
+ /* BRANCH has no proper alignment chain set, so use SEQ. */
if (INSN_SHUID (branch) < INSN_SHUID (dest))
{
/* Forward branch. */
return (insn_last_address + insn_lengths[seq_uid]
- - align_fuzz (branch, dest, length_unit_log, ~0));
+ - align_fuzz (seq, dest, length_unit_log, ~0));
}
else
{
/* Backward branch. */
return (insn_current_address
- + align_fuzz (dest, branch, length_unit_log, ~0));
+ + align_fuzz (dest, seq, length_unit_log, ~0));
}
}
#endif /* HAVE_ATTR_length */
rtx insn;
int max_uid;
int i;
- int max_labelno;
int max_log;
+ int max_skip;
#ifdef HAVE_ATTR_length
#define MAX_CODE_ALIGN 16
rtx seq;
/* We must do some computations even when not actually shortening, in
order to get the alignment information for the labels. */
+ init_insn_lengths ();
+
/* Compute maximum UID and allocate label_align / uid_shuid. */
max_uid = get_max_uid ();
max_labelno = max_label_num ();
min_labelno = get_first_label_num ();
- if (label_align)
- free (label_align);
- label_align
- = (short*) xmalloc ((max_labelno - min_labelno + 1) * sizeof (short));
- bzero (label_align, (max_labelno - min_labelno + 1) * sizeof (short));
+ label_align = (struct label_alignment *) xmalloc (
+ (max_labelno - min_labelno + 1) * sizeof (struct label_alignment));
+ bzero ((char *) label_align,
+ (max_labelno - min_labelno + 1) * sizeof (struct label_alignment));
- if (uid_shuid)
- free (uid_shuid);
uid_shuid = (int *) xmalloc (max_uid * sizeof *uid_shuid);
/* Initialize label_align and set up uid_shuid to be strictly
monotonically rising with insn order. */
- for (max_log = 0, insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn))
+ /* We use max_log here to keep track of the maximum alignment we want to
+ impose on the next CODE_LABEL (or the current one if we are processing
+ the CODE_LABEL itself). */
+
+ max_log = 0;
+ max_skip = 0;
+
+ for (insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn))
{
int log;
INSN_SHUID (insn) = i++;
if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
- max_log = 0;
+ {
+ /* reorg might make the first insn of a loop being run once only,
+ and delete the label in front of it. Then we want to apply
+ the loop alignment to the new label created by reorg, which
+ is separated by the former loop start insn from the
+ NOTE_INSN_LOOP_BEG. */
+ }
else if (GET_CODE (insn) == CODE_LABEL)
{
rtx next;
log = LABEL_ALIGN (insn);
if (max_log < log)
- max_log = log;
- next = NEXT_INSN (insn);
-/* ADDR_VECs only take room if read-only data goes into the text section. */
-#if !defined(READONLY_DATA_SECTION) || defined(JUMP_TABLES_IN_TEXT_SECTION)
- if (next && GET_CODE (next) == JUMP_INSN)
{
- rtx nextbody = PATTERN (next);
- if (GET_CODE (nextbody) == ADDR_VEC
- || GET_CODE (nextbody) == ADDR_DIFF_VEC)
- {
- log = ADDR_VEC_ALIGN (next);
- if (max_log < log)
- max_log = log;
- }
+ max_log = log;
+ max_skip = LABEL_ALIGN_MAX_SKIP;
}
-#endif
+ next = NEXT_INSN (insn);
+ /* ADDR_VECs only take room if read-only data goes into the text
+ section. */
+ if (JUMP_TABLES_IN_TEXT_SECTION
+#if !defined(READONLY_DATA_SECTION)
+ || 1
+#endif
+ )
+ if (next && GET_CODE (next) == JUMP_INSN)
+ {
+ rtx nextbody = PATTERN (next);
+ if (GET_CODE (nextbody) == ADDR_VEC
+ || GET_CODE (nextbody) == ADDR_DIFF_VEC)
+ {
+ log = ADDR_VEC_ALIGN (next);
+ if (max_log < log)
+ {
+ max_log = log;
+ max_skip = LABEL_ALIGN_MAX_SKIP;
+ }
+ }
+ }
LABEL_TO_ALIGNMENT (insn) = max_log;
+ LABEL_TO_MAX_SKIP (insn) = max_skip;
max_log = 0;
+ max_skip = 0;
}
else if (GET_CODE (insn) == BARRIER)
{
{
log = LABEL_ALIGN_AFTER_BARRIER (insn);
if (max_log < log)
- max_log = log;
+ {
+ max_log = log;
+ max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP;
+ }
break;
}
}
+ /* Again, we allow NOTE_INSN_LOOP_BEG - INSN - CODE_LABEL
+ sequences in order to handle reorg output efficiently. */
else if (GET_CODE (insn) == NOTE
&& NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
{
rtx label;
- for (label = insn; label && GET_RTX_CLASS (GET_CODE (label)) != 'i';
- label = NEXT_INSN (label))
+ for (label = insn; label; label = NEXT_INSN (label))
if (GET_CODE (label) == CODE_LABEL)
{
log = LOOP_ALIGN (insn);
if (max_log < log)
- max_log = log;
+ {
+ max_log = log;
+ max_skip = LOOP_ALIGN_MAX_SKIP;
+ }
break;
}
}
#ifdef HAVE_ATTR_length
/* Allocate the rest of the arrays. */
- if (insn_lengths)
- free (insn_lengths);
insn_lengths = (short *) xmalloc (max_uid * sizeof (short));
- if (insn_addresses)
- free (insn_addresses);
insn_addresses = (int *) xmalloc (max_uid * sizeof (int));
- if (uid_align)
- free (uid_align);
+ /* Syntax errors can lead to labels being outside of the main insn stream.
+ Initialize insn_addresses, so that we get reproducible results. */
+ bzero ((char *)insn_addresses, max_uid * sizeof *insn_addresses);
uid_align = (rtx *) xmalloc (max_uid * sizeof *uid_align);
varying_length = (char *) xmalloc (max_uid * sizeof (char));
for (i = MAX_CODE_ALIGN; --i >= 0; )
align_tab[i] = NULL_RTX;
seq = get_last_insn ();
- for (insn_current_address = 0; seq; seq = PREV_INSN (seq))
+ for (; seq; seq = PREV_INSN (seq))
{
int uid = INSN_UID (seq);
int log;
- int length_align;
log = (GET_CODE (seq) == CODE_LABEL ? LABEL_TO_ALIGNMENT (seq) : 0);
uid_align[uid] = align_tab[0];
- insn_addresses[uid] = --insn_current_address;
if (log)
{
/* Found an alignment label. */
for (i = log - 1; i >= 0; i--)
align_tab[i] = seq;
}
- if (GET_CODE (seq) != INSN || GET_CODE (PATTERN (seq)) != SEQUENCE)
- insn = seq;
- else
+ }
+#ifdef CASE_VECTOR_SHORTEN_MODE
+ if (optimize)
+ {
+ /* Look for ADDR_DIFF_VECs, and initialize their minimum and maximum
+ label fields. */
+
+ int min_shuid = INSN_SHUID (get_insns ()) - 1;
+ int max_shuid = INSN_SHUID (get_last_insn ()) + 1;
+ int rel;
+
+ for (insn = first; insn != 0; insn = NEXT_INSN (insn))
{
- insn = XVECEXP (PATTERN (seq), 0, 0);
- uid = INSN_UID (insn);
+ rtx min_lab = NULL_RTX, max_lab = NULL_RTX, pat;
+ int len, i, min, max, insn_shuid;
+ int min_align;
+ addr_diff_vec_flags flags;
+
+ if (GET_CODE (insn) != JUMP_INSN
+ || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
+ continue;
+ pat = PATTERN (insn);
+ len = XVECLEN (pat, 1);
+ if (len <= 0)
+ abort ();
+ min_align = MAX_CODE_ALIGN;
+ for (min = max_shuid, max = min_shuid, i = len - 1; i >= 0; i--)
+ {
+ rtx lab = XEXP (XVECEXP (pat, 1, i), 0);
+ int shuid = INSN_SHUID (lab);
+ if (shuid < min)
+ {
+ min = shuid;
+ min_lab = lab;
+ }
+ if (shuid > max)
+ {
+ max = shuid;
+ max_lab = lab;
+ }
+ if (min_align > LABEL_TO_ALIGNMENT (lab))
+ min_align = LABEL_TO_ALIGNMENT (lab);
+ }
+ XEXP (pat, 2) = gen_rtx_LABEL_REF (VOIDmode, min_lab);
+ XEXP (pat, 3) = gen_rtx_LABEL_REF (VOIDmode, max_lab);
+ insn_shuid = INSN_SHUID (insn);
+ rel = INSN_SHUID (XEXP (XEXP (pat, 0), 0));
+ flags.min_align = min_align;
+ flags.base_after_vec = rel > insn_shuid;
+ flags.min_after_vec = min > insn_shuid;
+ flags.max_after_vec = max > insn_shuid;
+ flags.min_after_base = min > rel;
+ flags.max_after_base = max > rel;
+ ADDR_DIFF_VEC_FLAGS (pat) = flags;
}
}
+#endif /* CASE_VECTOR_SHORTEN_MODE */
/* Compute initial lengths, addresses, and varying flags for each insn. */
if (log)
{
int align = 1 << log;
- int new_address = insn_current_address + align - 1 & -align;
+ int new_address = (insn_current_address + align - 1) & -align;
insn_lengths[uid] = new_address - insn_current_address;
insn_current_address = new_address;
}
body = PATTERN (insn);
if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
- ; /* This should be handled by LABEL_ALIGN. */
+ {
+ /* This only takes room if read-only data goes into the text
+ section. */
+ if (JUMP_TABLES_IN_TEXT_SECTION
+#if !defined(READONLY_DATA_SECTION)
+ || 1
+#endif
+ )
+ insn_lengths[uid] = (XVECLEN (body,
+ GET_CODE (body) == ADDR_DIFF_VEC)
+ * GET_MODE_SIZE (GET_MODE (body)));
+ /* Alignment is handled by ADDR_VEC_ALIGN. */
+ }
else if (asm_noperands (body) >= 0)
insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn);
else if (GET_CODE (body) == SEQUENCE)
insn = NEXT_INSN (insn))
{
int new_length;
-#ifdef SHORTEN_WITH_ADJUST_INSN_LENGTH
#ifdef ADJUST_INSN_LENGTH
int tmp_length;
#endif
-#endif
int length_align;
uid = INSN_UID (insn);
if (log > insn_current_align)
{
int align = 1 << log;
- int new_address= insn_current_address + align - 1 & -align;
+ int new_address= (insn_current_address + align - 1) & -align;
insn_lengths[uid] = new_address - insn_current_address;
insn_current_align = log;
insn_current_address = new_address;
insn_last_address = insn_addresses[uid];
insn_addresses[uid] = insn_current_address;
- if (! varying_length[uid])
+#ifdef CASE_VECTOR_SHORTEN_MODE
+ if (optimize && GET_CODE (insn) == JUMP_INSN
+ && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
+ {
+ rtx body = PATTERN (insn);
+ int old_length = insn_lengths[uid];
+ rtx rel_lab = XEXP (XEXP (body, 0), 0);
+ rtx min_lab = XEXP (XEXP (body, 2), 0);
+ rtx max_lab = XEXP (XEXP (body, 3), 0);
+ addr_diff_vec_flags flags = ADDR_DIFF_VEC_FLAGS (body);
+ int rel_addr = insn_addresses[INSN_UID (rel_lab)];
+ int min_addr = insn_addresses[INSN_UID (min_lab)];
+ int max_addr = insn_addresses[INSN_UID (max_lab)];
+ rtx prev;
+ int rel_align = 0;
+
+ /* Try to find a known alignment for rel_lab. */
+ for (prev = rel_lab;
+ prev
+ && ! insn_lengths[INSN_UID (prev)]
+ && ! (varying_length[INSN_UID (prev)] & 1);
+ prev = PREV_INSN (prev))
+ if (varying_length[INSN_UID (prev)] & 2)
+ {
+ rel_align = LABEL_TO_ALIGNMENT (prev);
+ break;
+ }
+
+ /* See the comment on addr_diff_vec_flags in rtl.h for the
+ meaning of the flags values. base: REL_LAB vec: INSN */
+ /* Anything after INSN has still addresses from the last
+ pass; adjust these so that they reflect our current
+ estimate for this pass. */
+ if (flags.base_after_vec)
+ rel_addr += insn_current_address - insn_last_address;
+ if (flags.min_after_vec)
+ min_addr += insn_current_address - insn_last_address;
+ if (flags.max_after_vec)
+ max_addr += insn_current_address - insn_last_address;
+ /* We want to know the worst case, i.e. lowest possible value
+ for the offset of MIN_LAB. If MIN_LAB is after REL_LAB,
+ its offset is positive, and we have to be wary of code shrink;
+ otherwise, it is negative, and we have to be vary of code
+ size increase. */
+ if (flags.min_after_base)
+ {
+ /* If INSN is between REL_LAB and MIN_LAB, the size
+ changes we are about to make can change the alignment
+ within the observed offset, therefore we have to break
+ it up into two parts that are independent. */
+ if (! flags.base_after_vec && flags.min_after_vec)
+ {
+ min_addr -= align_fuzz (rel_lab, insn, rel_align, 0);
+ min_addr -= align_fuzz (insn, min_lab, 0, 0);
+ }
+ else
+ min_addr -= align_fuzz (rel_lab, min_lab, rel_align, 0);
+ }
+ else
+ {
+ if (flags.base_after_vec && ! flags.min_after_vec)
+ {
+ min_addr -= align_fuzz (min_lab, insn, 0, ~0);
+ min_addr -= align_fuzz (insn, rel_lab, 0, ~0);
+ }
+ else
+ min_addr -= align_fuzz (min_lab, rel_lab, 0, ~0);
+ }
+ /* Likewise, determine the highest lowest possible value
+ for the offset of MAX_LAB. */
+ if (flags.max_after_base)
+ {
+ if (! flags.base_after_vec && flags.max_after_vec)
+ {
+ max_addr += align_fuzz (rel_lab, insn, rel_align, ~0);
+ max_addr += align_fuzz (insn, max_lab, 0, ~0);
+ }
+ else
+ max_addr += align_fuzz (rel_lab, max_lab, rel_align, ~0);
+ }
+ else
+ {
+ if (flags.base_after_vec && ! flags.max_after_vec)
+ {
+ max_addr += align_fuzz (max_lab, insn, 0, 0);
+ max_addr += align_fuzz (insn, rel_lab, 0, 0);
+ }
+ else
+ max_addr += align_fuzz (max_lab, rel_lab, 0, 0);
+ }
+ PUT_MODE (body, CASE_VECTOR_SHORTEN_MODE (min_addr - rel_addr,
+ max_addr - rel_addr,
+ body));
+ if (JUMP_TABLES_IN_TEXT_SECTION
+#if !defined(READONLY_DATA_SECTION)
+ || 1
+#endif
+ )
+ {
+ insn_lengths[uid]
+ = (XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)));
+ insn_current_address += insn_lengths[uid];
+ if (insn_lengths[uid] != old_length)
+ something_changed = 1;
+ }
+
+ continue;
+ }
+#endif /* CASE_VECTOR_SHORTEN_MODE */
+
+ if (! (varying_length[uid]))
{
insn_current_address += insn_lengths[uid];
continue;
insn_current_address += new_length;
}
-#ifdef SHORTEN_WITH_ADJUST_INSN_LENGTH
#ifdef ADJUST_INSN_LENGTH
/* If needed, do any adjustment. */
tmp_length = new_length;
ADJUST_INSN_LENGTH (insn, new_length);
insn_current_address += (new_length - tmp_length);
#endif
-#endif
if (new_length != insn_lengths[uid])
{
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (!call_used_regs[i] && !call_fixed_regs[i])
+ if (!call_used_regs[i])
regs_ever_live[i] = 1;
}
#endif
{
register rtx insn;
int max_line = 0;
+ int max_uid = 0;
last_ignored_compare = 0;
new_block = 1;
bzero (line_note_exists, max_line + 1);
for (insn = first; insn; insn = NEXT_INSN (insn))
- if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
- line_note_exists[NOTE_LINE_NUMBER (insn)] = 1;
+ {
+ if (INSN_UID (insn) > max_uid) /* find largest UID */
+ max_uid = INSN_UID (insn);
+ if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
+ line_note_exists[NOTE_LINE_NUMBER (insn)] = 1;
+#ifdef HAVE_cc0
+ /* If CC tracking across branches is enabled, record the insn which
+ jumps to each branch only reached from one place. */
+ if (optimize && GET_CODE (insn) == JUMP_INSN)
+ {
+ rtx lab = JUMP_LABEL (insn);
+ if (lab && LABEL_NUSES (lab) == 1)
+ {
+ LABEL_REFS (lab) = insn;
+ }
+ }
+#endif
+ }
+
+ /* Initialize insn_eh_region table if eh is being used. */
+
+ init_insn_eh_region (first, max_uid);
init_recog ();
if the last insn was a conditional branch. */
if (profile_block_flag && new_block)
add_bb (file);
+
+ free_insn_eh_region ();
}
\f
/* The final scan for one insn, INSN.
&& ! exceptions_via_longjmp)
{
ASM_OUTPUT_INTERNAL_LABEL (file, "LEHB", NOTE_BLOCK_NUMBER (insn));
- add_eh_table_entry (NOTE_BLOCK_NUMBER (insn));
+ if (! flag_new_exceptions)
+ add_eh_table_entry (NOTE_BLOCK_NUMBER (insn));
#ifdef ASM_OUTPUT_EH_REGION_BEG
ASM_OUTPUT_EH_REGION_BEG (file, NOTE_BLOCK_NUMBER (insn));
#endif
&& ! exceptions_via_longjmp)
{
ASM_OUTPUT_INTERNAL_LABEL (file, "LEHE", NOTE_BLOCK_NUMBER (insn));
+ if (flag_new_exceptions)
+ add_eh_table_entry (NOTE_BLOCK_NUMBER (insn));
#ifdef ASM_OUTPUT_EH_REGION_END
ASM_OUTPUT_EH_REGION_END (file, NOTE_BLOCK_NUMBER (insn));
#endif
PENDING_BLOCKS and output debugging info based on that. */
--block_depth;
+ if (block_depth < 0)
+ abort ();
#ifdef XCOFF_DEBUGGING_INFO
- if (write_symbols == XCOFF_DEBUG && block_depth >= 0)
+ if (write_symbols == XCOFF_DEBUG)
xcoffout_end_block (file, high_block_linenum,
pending_blocks[block_depth]);
#endif
#ifdef DBX_DEBUGGING_INFO
- if (write_symbols == DBX_DEBUG && block_depth >= 0)
+ if (write_symbols == DBX_DEBUG)
ASM_OUTPUT_INTERNAL_LABEL (file, "LBE",
pending_blocks[block_depth]);
#endif
#ifdef SDB_DEBUGGING_INFO
- if (write_symbols == SDB_DEBUG && block_depth >= 0)
+ if (write_symbols == SDB_DEBUG)
sdbout_end_block (file, high_block_linenum,
pending_blocks[block_depth]);
#endif
#ifdef DWARF_DEBUGGING_INFO
- if (write_symbols == DWARF_DEBUG && block_depth >= 0)
+ if (write_symbols == DWARF_DEBUG)
dwarfout_end_block (pending_blocks[block_depth]);
#endif
#ifdef DWARF2_DEBUGGING_INFO
- if (write_symbols == DWARF2_DEBUG && block_depth >= 0)
+ if (write_symbols == DWARF2_DEBUG)
dwarf2out_end_block (pending_blocks[block_depth]);
#endif
}
break;
case CODE_LABEL:
- {
- int align = LABEL_TO_ALIGNMENT (insn);
+ /* The target port might emit labels in the output function for
+ some insn, e.g. sh.c output_branchy_insn. */
+ if (CODE_LABEL_NUMBER (insn) <= max_labelno)
+ {
+ int align = LABEL_TO_ALIGNMENT (insn);
+#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
+ int max_skip = LABEL_TO_MAX_SKIP (insn);
+#endif
- if (align && NEXT_INSN (insn))
- ASM_OUTPUT_ALIGN (file, align);
- }
+ if (align && NEXT_INSN (insn))
+#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
+ ASM_OUTPUT_MAX_SKIP_ALIGN (file, align, max_skip);
+#else
+ ASM_OUTPUT_ALIGN (file, align);
+#endif
+ }
+#ifdef HAVE_cc0
CC_STATUS_INIT;
+ /* If this label is reached from only one place, set the condition
+ codes from the instruction just before the branch. */
+
+ /* Disabled because some insns set cc_status in the C output code
+ and NOTICE_UPDATE_CC alone can set incorrect status. */
+ if (0 /* optimize && LABEL_NUSES (insn) == 1*/)
+ {
+ rtx jump = LABEL_REFS (insn);
+ rtx barrier = prev_nonnote_insn (insn);
+ rtx prev;
+ /* If the LABEL_REFS field of this label has been set to point
+ at a branch, the predecessor of the branch is a regular
+ insn, and that branch is the only way to reach this label,
+ set the condition codes based on the branch and its
+ predecessor. */
+ if (barrier && GET_CODE (barrier) == BARRIER
+ && jump && GET_CODE (jump) == JUMP_INSN
+ && (prev = prev_nonnote_insn (jump))
+ && GET_CODE (prev) == INSN)
+ {
+ NOTICE_UPDATE_CC (PATTERN (prev), prev);
+ NOTICE_UPDATE_CC (PATTERN (jump), jump);
+ }
+ }
+#endif
if (prescan > 0)
break;
new_block = 1;
if (GET_CODE (nextbody) == ADDR_VEC
|| GET_CODE (nextbody) == ADDR_DIFF_VEC)
{
-#ifndef JUMP_TABLES_IN_TEXT_SECTION
- readonly_data_section ();
+#if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
+ /* In this case, the case vector is being moved by the
+ target, so don't output the label at all. Leave that
+ to the back end macros. */
+#else
+ if (! JUMP_TABLES_IN_TEXT_SECTION)
+ {
+ readonly_data_section ();
#ifdef READONLY_DATA_SECTION
- ASM_OUTPUT_ALIGN (file,
- exact_log2 (BIGGEST_ALIGNMENT
- / BITS_PER_UNIT));
+ ASM_OUTPUT_ALIGN (file,
+ exact_log2 (BIGGEST_ALIGNMENT
+ / BITS_PER_UNIT));
#endif /* READONLY_DATA_SECTION */
-#else /* JUMP_TABLES_IN_TEXT_SECTION */
- function_section (current_function_decl);
-#endif /* JUMP_TABLES_IN_TEXT_SECTION */
+ }
+ else
+ function_section (current_function_decl);
+
#ifdef ASM_OUTPUT_CASE_LABEL
ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn),
NEXT_INSN (insn));
#else
ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (insn));
#endif
+#endif
break;
}
}
if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
{
+#if !(defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC))
register int vlen, idx;
+#endif
if (prescan > 0)
break;
app_on = 0;
}
+#if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
+ if (GET_CODE (body) == ADDR_VEC)
+ {
+#ifdef ASM_OUTPUT_ADDR_VEC
+ ASM_OUTPUT_ADDR_VEC (PREV_INSN (insn), body);
+#else
+ abort();
+#endif
+ }
+ else
+ {
+#ifdef ASM_OUTPUT_ADDR_DIFF_VEC
+ ASM_OUTPUT_ADDR_DIFF_VEC (PREV_INSN (insn), body);
+#else
+ abort();
+#endif
+ }
+#else
vlen = XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC);
for (idx = 0; idx < vlen; idx++)
{
#ifdef ASM_OUTPUT_ADDR_DIFF_ELT
ASM_OUTPUT_ADDR_DIFF_ELT
(file,
+ body,
CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0)));
#else
CODE_LABEL_NUMBER (PREV_INSN (insn)),
insn);
#endif
+#endif
function_section (current_function_decl);
/* Detect `asm' construct with operands. */
if (asm_noperands (body) >= 0)
{
- int noperands = asm_noperands (body);
+ unsigned int noperands = asm_noperands (body);
rtx *ops = (rtx *) alloca (noperands * sizeof (rtx));
char *string;
since `reload' should have changed them so that they do. */
insn_code_number = recog_memoized (insn);
- insn_extract (insn);
- for (i = 0; i < insn_n_operands[insn_code_number]; i++)
- {
- if (GET_CODE (recog_operand[i]) == SUBREG)
- recog_operand[i] = alter_subreg (recog_operand[i]);
- else if (GET_CODE (recog_operand[i]) == PLUS
- || GET_CODE (recog_operand[i]) == MULT)
- recog_operand[i] = walk_alter_subreg (recog_operand[i]);
- }
-
- for (i = 0; i < insn_n_dups[insn_code_number]; i++)
- {
- if (GET_CODE (*recog_dup_loc[i]) == SUBREG)
- *recog_dup_loc[i] = alter_subreg (*recog_dup_loc[i]);
- else if (GET_CODE (*recog_dup_loc[i]) == PLUS
- || GET_CODE (*recog_dup_loc[i]) == MULT)
- *recog_dup_loc[i] = walk_alter_subreg (*recog_dup_loc[i]);
- }
+ extract_insn (insn);
+ cleanup_subreg_operands (insn);
#ifdef REGISTER_CONSTRAINTS
- if (! constrain_operands (insn_code_number, 1))
+ if (! constrain_operands (1))
fatal_insn_not_found (insn);
#endif
it is output. */
#ifdef FINAL_PRESCAN_INSN
- FINAL_PRESCAN_INSN (insn, recog_operand,
- insn_n_operands[insn_code_number]);
+ FINAL_PRESCAN_INSN (insn, recog_operand, recog_n_operands);
#endif
#ifdef HAVE_cc0
/* If we didn't split the insn, go away. */
if (new == insn && PATTERN (new) == body)
- abort ();
+ fatal_insn ("Could not split insn", insn);
#ifdef HAVE_ATTR_length
/* This instruction should have been split in shorten_branches,
}
}
\f
+
+/* For each operand in INSN, simplify (subreg (reg)) so that it refers
+ directly to the desired hard register. */
+void
+cleanup_subreg_operands (insn)
+ rtx insn;
+{
+ int i;
+
+ extract_insn (insn);
+ for (i = 0; i < recog_n_operands; i++)
+ {
+ if (GET_CODE (recog_operand[i]) == SUBREG)
+ recog_operand[i] = alter_subreg (recog_operand[i]);
+ else if (GET_CODE (recog_operand[i]) == PLUS
+ || GET_CODE (recog_operand[i]) == MULT)
+ recog_operand[i] = walk_alter_subreg (recog_operand[i]);
+ }
+
+ for (i = 0; i < recog_n_dups; i++)
+ {
+ if (GET_CODE (*recog_dup_loc[i]) == SUBREG)
+ *recog_dup_loc[i] = alter_subreg (*recog_dup_loc[i]);
+ else if (GET_CODE (*recog_dup_loc[i]) == PLUS
+ || GET_CODE (*recog_dup_loc[i]) == MULT)
+ *recog_dup_loc[i] = walk_alter_subreg (*recog_dup_loc[i]);
+ }
+}
+
/* If X is a SUBREG, replace it with a REG or a MEM,
based on the thing it is a subreg of. */
register rtx x;
{
register rtx y = SUBREG_REG (x);
+
if (GET_CODE (y) == SUBREG)
y = alter_subreg (y);
+ /* If reload is operating, we may be replacing inside this SUBREG.
+ Check for that and make a new one if so. */
+ if (reload_in_progress && find_replacement (&SUBREG_REG (x)) != 0)
+ x = copy_rtx (x);
+
if (GET_CODE (y) == REG)
{
- /* If the containing reg really gets a hard reg, so do we. */
+ /* If the word size is larger than the size of this register,
+ adjust the register number to compensate. */
+ /* ??? Note that this just catches stragglers created by/for
+ integrate. It would be better if we either caught these
+ earlier, or kept _all_ subregs until now and eliminate
+ gen_lowpart and friends. */
+
PUT_CODE (x, REG);
+#ifdef ALTER_HARD_SUBREG
+ REGNO (x) = ALTER_HARD_SUBREG(GET_MODE (x), SUBREG_WORD (x),
+ GET_MODE (y), REGNO (y));
+#else
REGNO (x) = REGNO (y) + SUBREG_WORD (x);
+#endif
+ /* This field has a different meaning for REGs and SUBREGs. Make sure
+ to clear it! */
+ x->used = 0;
}
else if (GET_CODE (y) == MEM)
{
- MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (y))));
PUT_CODE (x, MEM);
MEM_VOLATILE_P (x) = MEM_VOLATILE_P (y);
+ MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (y);
+ MEM_ALIAS_SET (x) = MEM_ALIAS_SET (y);
XEXP (x, 0) = plus_constant (XEXP (y, 0), offset);
}
if (this_is_asm_operands)
error_for_asm (this_is_asm_operands, "invalid `asm': %s", str);
else
- abort ();
+ fatal ("Internal compiler error, output_operand_lossage `%s'", str);
}
\f
/* Output of assembler code from a template, and its subroutines. */
if (debug_insn)
{
register int num = INSN_CODE (debug_insn);
- fprintf (asm_out_file, " %s %d %s",
+ fprintf (asm_out_file, "\t%s %d\t%s",
ASM_COMMENT_START, INSN_UID (debug_insn), insn_name[num]);
if (insn_n_alternatives[num] > 1)
fprintf (asm_out_file, "/%d", which_alternative + 1);
-
+#ifdef HAVE_ATTR_length
+ fprintf (asm_out_file, "\t[length = %d]", get_attr_length (debug_insn));
+#endif
/* Clear this so only the first assembler insn
of any rtl insn will get the special comment for -dp. */
debug_insn = 0;
if (! (*p >= '0' && *p <= '9'))
output_operand_lossage ("operand number missing after %-letter");
- else if (this_is_asm_operands && c >= (unsigned) insn_noperands)
+ else if (this_is_asm_operands && (c < 0 || (unsigned int) c >= insn_noperands))
output_operand_lossage ("operand number out of range");
else if (letter == 'l')
output_asm_label (operands[c]);
else if (*p >= '0' && *p <= '9')
{
c = atoi (p);
- if (this_is_asm_operands && c >= (unsigned) insn_noperands)
+ if (this_is_asm_operands && (c < 0 || (unsigned int) c >= insn_noperands))
output_operand_lossage ("operand number out of range");
else
output_operand (operands[c], 0);
void
asm_fprintf VPROTO((FILE *file, char *p, ...))
{
-#ifndef __STDC__
+#ifndef ANSI_PROTOTYPES
FILE *file;
char *p;
#endif
VA_START (argptr, p);
-#ifndef __STDC__
+#ifndef ANSI_PROTOTYPES
file = va_arg (argptr, FILE *);
p = va_arg (argptr, char *);
#endif
break;
case 'U':
-#ifdef USER_LABEL_PREFIX
- fprintf (file, "%s", USER_LABEL_PREFIX);
-#endif
+ fputs (user_label_prefix, file);
break;
default:
if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
{
/* In this case the CONST_INT holds both target words.
- Extract the bits from it into two word-sized pieces. */
+ Extract the bits from it into two word-sized pieces.
+ Sign extend each half to HOST_WIDE_INT. */
rtx low, high;
- HOST_WIDE_INT word_mask;
- /* Avoid warnings for shift count >= BITS_PER_WORD. */
- int shift_count = BITS_PER_WORD - 1;
-
- word_mask = (HOST_WIDE_INT) 1 << shift_count;
- word_mask |= word_mask - 1;
- low = GEN_INT (INTVAL (value) & word_mask);
- high = GEN_INT ((INTVAL (value) >> (shift_count + 1)) & word_mask);
+ /* On machines where HOST_BITS_PER_WIDE_INT == BITS_PER_WORD
+ the shift below will cause a compiler warning, even though
+ this code won't be executed. So put the shift amounts in
+ variables to avoid the warning. */
+ int rshift = HOST_BITS_PER_WIDE_INT - BITS_PER_WORD;
+ int lshift = HOST_BITS_PER_WIDE_INT - 2 * BITS_PER_WORD;
+
+ low = GEN_INT ((INTVAL (value) << rshift) >> rshift);
+ high = GEN_INT ((INTVAL (value) << lshift) >> rshift);
if (WORDS_BIG_ENDIAN)
{
*first = high;
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- {
- if ((regs_ever_live[i] || global_regs[i])
- && ! permitted_reg_in_leaf_functions[i])
- return 0;
- }
+ if ((regs_ever_live[i] || global_regs[i])
+ && ! permitted_reg_in_leaf_functions[i])
+ return 0;
+
+ if (current_function_uses_pic_offset_table
+ && pic_offset_table_rtx != 0
+ && GET_CODE (pic_offset_table_rtx) == REG
+ && ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)])
+ return 0;
+
return 1;
}
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